Slide 19 of 64
Notes:
This slide shows the waveforms of the relatively slow risetime TTL compatible signals from the Xilinx CMOS chip and the outputs of the pin drivers going to the GaAs pad receivers on the Boundary Scan test inputs on the chips. After shifting in a set of inputs, a single 4 phase clock sequence is spun up on each chip providing the capability to test each chip at speed for harvesting for KGD selection.