Slide 22 of 64
The left hand side of this slide shows an optical micrograph of the "RPI Test Chip" which has been used repeatedly as a probe to characterize the Rockwell 50 GHz Baseline Process directly by monitoring digital circuit speed and yield. It contains the actual 32 word x 8 bit register file for the Fast RISC with some LFSR circuits to test it at speed. The lower part of the chip contains an adder carry chain ring oscillator designed to pin down the speed of the adder. The TEK 7104 oscilloscope output with TDR sampling for the 2.5 GHz LFSR address generator is shown on the right side. This is a pseudo random address generator, with a similar circuit for pseudo random data generation. All F-RISC circuits must contain all the circuitry to test themselves comprehensively at GHz speed. There are few commercial testers at these frequencies.