Slide 24 of 64
The HBT circuit on the left was designed to be a clock driver for 10 GHz I/O channels for F-RISC and represented a design challenge since it operates with many HBTs at a significant fraction of the maximum transition frequency of 50 GHz. Many important lessons were learned by designing this circuit, including recognizing the filtering effect of the distributed RC wiring bandwidth on harmonics. A core ring oscillator was quadrupled with a digital multiplier to reach an observed speed of 13.7 GHz. Predicted speed was 20 GHz.