Slide 27 of 64
To make the discussion more spirited let us compare three generations of CMOS. The data here are from the SIA roadmap. Note that while the delay power product is approximately shrinking linearly with the scaling factor to numbers like 100 fJ/gate, the clock rate is going up linearly. Hence the total power is staying the same!
Worse yet the power density is going up. In fact, it is going up as the square of the scale factor! Shrinking power supply voltages does help, and this is reflected in the lower power gate numbers. But there is a limit to how much of this is possible, otherwise we'd be doing it right now.