Slide 29 of 64
We now turn our attention to the future, the next generation of HBTs and where that may lead. We expect that 100 GHz HBT processes will emerge, and that if this is accompanied with smaller emitter stripes, better device yields, and better interconnection processes (for wire delay management), that processors will emerge that can support clock rates as high as several 10's of GHz. Implemented in VLIW superscalar format these engines could provide as much as 0.128 TeraOPS per processor. Eight of these on a board would provide 1.0 TeraOPS, and a PetaOPS machine would only require 1000 of these.