Slide 34 of 64
This slide shows a simplified VLIW superscalar architecture similar to the one we propose for implementation in 100 GHz SiGe HBT technology. Estimated clock speed is 16GHz based on existing building blocks. However, the HBT must be co-integrated with aggressive CMOS to provide for on chip L1 memory for each leg of the superscalar's pipeline system. SiGe is estimated to create the possibility of implementing this system at a power dissipation level of about 100 watts, including four way floating point processors, and dual integer pipes.