Slide 40 of 64
This a scanned image of the abstract for the Hitachi paper. It announces a power delay product is achieved of only 5.1 fJ/gate with 0.2 micron emitter stripe widths. This may be compared with recent generations of power delay products for CMOS, which are at best about a factor of 10 higher than this. At this point we cannot tell whether the trend can be made to continue because smaller emitter scaling is not presented. But the trend is in the right direction. Power dissipation for CML is mostly dictated by the Ic value for which the device achieves its peak fT value.