Slide 61 of 64
We would also be needing a 8 GHz adder in this technology. We are working on such an adder for inclusion in the next DARPA shared reticle run. We have established that the addition of two 32 bits numbers might be possible in just 5 CML block delays, or roughly 75 ps even in this 50 GHz baseline.
This means that 62 picosecond addition times are possible in any reasonable 100 GHz process.