F-RISC/G Final Reticle

Reg File Test

Cache Controller

Experimental

Device Structures

Datapath

Test Structures

VCOís

Cache RAM

Instruction

Decoder

Deskew PLL chip

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This is the GDSII final artwork file for the F-RISC/G as sent to Rockwell for fabrication. The byteslice DataPath or DP chip is to be replicated 4 times for the 32 bit architecture. Only the Register Files (RFs) are handcrafted. The Instruction Decoder