High-Speed Voltage Controlled Oscillator

New! VCO test results!

VCO Characteristics:

Background Information

In May of 1993, the development of a high-speed voltage controlled oscillator was begun as a "challenge circuit" to further explore the capabilities of our GaAs devices and foundry process. The premise of the project was simple: to develop a circuit which would oscillate as fast as possible with the frequency controllable by an applied voltage. The target maximum frequency was 20 GHz.

Design Information

The architecture of the VCO begins with a core of four delay elements cyclically connected with one inversion. A signal passing through the elements is inverted, producing an oscillating waveform. The frequency of oscillation may be adjusted by changing the control voltage applied to the delay elements. The core frequency ranges from 2 to 5 GHz.

A frequency multiplier consisting of three exclusive-OR (XOR) gates is capable of multiplying the core frequency by a factor or 2 or 4. The design of the multiplier cells is highly-dependent upon the matched capacitance of the differential signal paths. If the capacitance is too high, the cells will underperform. If the capacitance of each signal in the differential pair is significantly unsymmetrical, the skew between each conductor of the signal will be significant and the cells will again underperform. In order to observe the output of the VCO, a prescaler is included. The scaling factors available are 1, 2, 4, and 8. As with the frequency multiplier, the layout of the prescaler is critically dependent upon the matched capacitance of the circuit. There are other miscellaneous cells used in the VCO which are also critically important. These include 4-to-1 multiplexors and various high-gain differential amplifiers. As with the frequency multiplier and prescaler, matched parasitic capacitance is of primary importance in the design of the subcells.

Test Results

In March of 1995, we received a wafer which contained a copy of the VCO chip. Testing commenced immediately. We have had problems in the past with sub-nominal device and interconnect performance and were curious if we would see these problems again. For results and analysis, see VCO Test Results.

Matched-capacitance Layout of Differential Circuits

This section is still under construction.

Other work:
Please send comments and suggestions to:
Send mail to campbell@unix.cie.rpi.edu