Items of interest...
- Paper on high-speed VCO design at IEEE GaAs IC Symposium in San Diego...
- Preparations for doctoral candidacy exam are (still, slowly) progressing...
Work progressing this week...
- LVS checking of Datapath chip with changes to the carry-chain,
register file, power rails, pad ring, and Steve Carlough's fixes...
- LVS checking of Datapath chip with changes to carry-chain, register file, and Steve Carlough's fixes...passed on June 30...
- Generation of backannotated PSPICE netlists of carry chain...
- Development of theoretical investigations for thesis...
- Description of high-speed VCO testing results for ARPA Spring 1995 Semiannual...
- Comparison of VCO test results with backannotated PSPICE simulations...
- MASKAP Layout-Versus-Schematics (LVS) checking of Datapath Registerfile
- Paper on high-speed VCO / matched-capacitance layout accepted at
ASIC'95 in Houston...
Datapath Chip Registerfile Modifications
The registerfile used within the datapath chip was never modified as
the testchip registerfile had been. The two cells are essentially the
same but the datapath version has a few additional features to make it
appear to be a dual-port memory.
The original registerfile was modified to reduce parasitic
capacitances within the circuit. Initially, the process we were using
had only two-levels of metallization available which made routing
signals somewhat complicated. When the process was modified to include
a third level of metallization, we were able to redesign the circuit
and reroute many signals. Another benefit was that capacitance between
the first and third levels of metallization was significantly lesser
than that of a metal 1 / metal 2 crossover. Finally, the third level
of metal could be routed over devices, allowing us to produce more
In order to improve the speed of the Datapath carry-chain, I optimized
the layout of the circuit and extracted a SPICE netlist for
simulation. We removed a level-shifter from the input of the
carry-chain and left the output on level 2.
Datapath Wiring Modifications
After the power rails and pad ring were modified to reduce chip area, the standard cell areas were moved around a bit to squeeze them closer together. In addition, I went through the standard cell areas and cleaned up unnecessary crossovers produced by cutter.
Datapath Chip Power Rail Modifications
In order to reduce the size of the chip and improve bypass
capacitance, the power-rail scheme was redesigned (mainly by Sam
Steidl). Metal 2 and metal 3 were placed vertically to improve bypass
capacitance and reduce chip area. The pad ring was then reduced.
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