F-RISC Testchip Redesign

Describing the original and redesigned F-RISC test chips...

Much of this information has been obtained from Bob Philhower's thesis Spartan RISC Architecture for Yield-Limited Technology

F-RISC Testchip


The design of a F-RISC testchip was begun in December 1991 in order to verify critical portions of the F-RISG/G processor and to learn more about the Rockwell 50 GHz GaAs HBT process. The circuits we wanted to check included a 32 x 8 register file, an 8-bit carry-chain (used in a binary adder), and other various standard cells which were used as support circuitry. The testchip uses about 2600 HBTs on a 3.2 mm x 3.4 mm die. Testing of the bare dies was to use a six-channel microwave probe. The signal limitations guided much of the testchip design. In order to reduce the signals required for testing, test signals were generated on-chip using linear feedback shift registers (LFSRs) and fed into the register file and carry-chain.

Testing Results

Register File

The first step in testing the register files were to determine which chips had functioning test circuitry, namely the voltage-controlled oscillator which generated clocking signals and the data and address LFSRs. About 50% of the 58 fabricated chips had working VCOs, however, only two of the chips had both LFSRs working. Unfortunately, of these two chips, only one chip had LFSRs which worked at the same VCO frequency and supply voltage. From this chip, we could determine that the registerfile, write circuit and match circuit were functional (pictures not available at this time).


The carry-chain was designed to oscillate using either of two paths through the circuit. The frequency of oscillation would indicate the speed of the circuit. We measured cycle times of 850ps and 475ps for the slow and fast oscillation paths.

Voltage-Controlled Oscillator (VCO)

The VCO consisted basically of four voltage-controlled delay elements which were connected as a ring oscillator. The target frequency of the VCO was between 1.5 GHz and 4.8 GHz, however, the actual frequencies were somewhat below this at about 2.5 GHz.

Linear Feedback Shift Registers (LFSRs)

The LFSRs were used to generate both data and address signals on-chip in order to simplify testing. Each circuit had 5 stages and was designed for a maximal sequence of 31-bits. Unfortunately, nearly none of the chips had both circuits functioning at the same clock frequency and supply voltage.


Linear Feedback Shift Registers

In order to improve the yield of the LFSRs, we boosted the power levels of the address LFSR from medium-power to high-power. The data LFSR was already high-powered and we hoped that having both circuits at equal power levels would have a better yield. We have fabricated and tested the new testchips but I don't have the new data yet. Reportedly, the LFSR yield has improved dramatically.

Power Rail Design

Between the time of the original design and the modifications, Rockwell introduced a third level of metallization into their process. This enabled us to improve the power-routing scheme by moving rails from metal 1 to metal 2 or 3 and by double-strapping metal on the rails to reduce voltage drops. Another modification was the addition of two touchdown pads on Vss/Vdd in the middle of the chip. These pads allow us to determine the voltage drop along the rails and see if the power-routing scheme is adequate.

Register File Threshold Voltage Tap

In order to gain more information about the register file circuitry, we added a single tap onto the threshold voltage generator signal.

Other work:

This page is still under construction, so I don't promise that anything will work properly!!!

Please send comments and suggestions to: campbell@unix.cie.rpi.edu