My PhD Thesis is on the design and implementation of high speed RISC processors. The current implementation is a 32-bit integer engine running at 1 Giga Hertz. The processor is implemented using GaAs/AlGaAs Hetero-junction Bipolar transistors (HBT). The next processor will be implemented using the SiGe BiCMOS processes at IBM. The target speed for that processor will exceed 10 GHz. The focus of my work is to optimize the performance of the processor using as few transistors as possible. Unlike CMOS processor which use millions of transistors per die, our resources are limited to less then 50,000.
Computer Hardware Design (Fall '93, Fall '94, Fall '97)
Advanced Computer Hardware Design (Spring '94, Spring '96, Spring '97)
Digital Electronics (Spring '94)
My Masters thesis involved verifying the top level netlist of the FRISC-G processor developed here at RPI. This verification is done using the digital simulator contained in the Viewlogic CAD tools. The design is routed to a test bed of programmable logic. This test bed is provided by an APTIX board. The APTIX board provides programmable interconnect between up to 21 XILINX Field Programmable Gate Arrays (FPGA). The original processor has been partitioned into multiple chips due to the yield limited nature of the technology. These chips are then interconnected using a high speed multichip module (MCM). A gate to gate mapping of each chip in the processor is mapped to one FPGA on the APTIX board. The MCM routing is then mapped to the Field Programmable Interconnect Components (FPIC) provided on the APTIX board. The result is a gate to gate mapping of the actual design in a reconfigurable test bed. This system is then used for code development for the processor, and design verification. My thesis describing this will be online here in the next few months. Question sent to me by email will be happily answered.
It seems someone actually cares about the work I've done and has decided to publish it!
Send mail to email@example.com