Matthew Ernest, Research Home Page

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Pseudo-Carry Lookahead

Carry Select Adder

The FRISC-G processor utilizes a carry-select adder. Each of 4 datapath chips contains an 8-bit carry select stage.

It was conjectured that for a hypothetical process with greater yield that the GaAs process utilized for FRISC-G the datapath could be placed on a single die. This would allow optimization of the stage sizes in the carry select scheme. I developed the design logic for such optimization, and created the circuit and layout for a 32-bit carry-select adder. The optimization drop the addition time from 12 to 9 gate delays.

This material was presented in the Spring '96 F-RISC Semi-Annual Report to DARPA, and was updated on 4/8/96.

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Copyright 2002, Matthew W. Ernest
(mernest@unix.cie.rpi.edu)
where applicable.
Last update: 10/14/2002; 11:32:19 PM. myURL=http://inp.cie.rpi.edu/~mernest/adders.html
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