FIGURE 2-2: Carry Select Adder 7
FIGURE 2-3: Flat Carry Look-ahead 8
FIGURE 2-4: Block Carry Look-ahead 8
FIGURE 4-1: Single-Ended Reference Current Switch 22
FIGURE 4-2: Differential Pair Current Switch 22
FIGURE 4-3: Arrangement of circuits in carry stages 24
FIGURE 4-4: Five bit select block from delay optimized carry select layout 27
FIGURE 4-5: SPICE simulation of delay optimized 32-bit carry select adder 28
FIGURE 4-6: Look-ahead gate constructed with fully-differential logic 29
FIGURE 4-7: Mixed single-ended and differential inputs for look-ahead gate 30
FIGURE 4-8: Blocks arranged in a pseudo-carry look-ahead tree 30
FIGURE 5-1: Carry tree test structure 31
FIGURE 5-2: Pseudo-carry test structure simulation 32
FIGURE 5-3: Example of carry look-ahead generation and distribution tree, from [BREN82] 34