1. Introduction

The F-RISC project is dedicated to the pursuit of high clock rates in RISC processor design, leveraging high-performance technologies[NAH91] in exchange for spartan architectures [PHIL93]. The project currently focuses on new components and design methodology for an intermediate 8 GHz clock rate with projected ramp up to 16 GHz RISC processors. To meet the cycle time limitations imposed, the goal of any design of a computational engine is that major functional units which comprise pipeline stages guarantee a maximum delay which is less than the allotted cycle time. The integer adder is one such major functional unit found at the core of almost any type of processor.

One pipeline stage in a RISC processor, for example, is typically devoted to the adder and its associated execution units. The carry circuitry of an adder typically comprises a critical path, i.e. a path that limits the speed of operation. The carry out of an adder possibly depends on every input, requiring a carefully crafted and optimized circuit. Often that optimization is carried out in terms of the mythical "gate delay". Of course, once the design gets down to the circuit level, actual per circuit timing information are used and efforts are made to minimize delay. However, if circuit behaviors and parasitics are accounted for at a higher level, this can lead to a much different optimization with improved performance under these degrading, i.e. real, circuit effects.

Two different kinds of adders have been the subject of this research so far. First, a carry select adder based on the original F-RISC/G adder [PHIL93] was examined, to optimize the adder delay based on varying the select stage sizes. When the 8GHz and 16GHz processor speeds were proposed, a move to pseudo-carry look-ahead was necessary to further reduce the propagation delay through the adder.