6. Bibliography

[BEDR62] O.J. Bedrij, "Carry-Select Adder", IRE Trans. On Electronic Computers, vol. EC-11 No. 3, pp. 340-346;June 1962.

[BREN82] R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders", IEEE Trans. on Computers, vol. C-31, no 3, pp 260-264. March 1982.

[EICH91] E. B. Eichelberger and S. E. Bello, "Differential current switch---High performance at low power", IBM Journal of Research and Development, Vol. 35 no. 3, pp 313-320. May 1991.

[HWAN79] K. Hwang, Computer Arithmetic: Principles, Architecture, and Design, John Wiley and Sons, New York, 1979.

[IEEE85] IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754-1985), IEEE Press, 1985

[LING66] H. Ling, "High-Speed Binary Parallel Adder", IEEE Trans. Electron. Computers EC-15. Vol. 15 no. 10, October 1966.

[LING81] H. Ling, "High-Speed Binary Adder", IBM Journal of Research and Development. Vol. 25 no. 3, May 1981.

[LYNC81] T. Lynch and E. Swartzlander, "A Spanning Tree Carry Lookahead Adder", IEEE Trans. Electron. Computers EC-41. Vol. 41 no. 8, October 1992.

[NAH91] K. Nah, R. Philhower, J.S. Van Etten, V. Tsinker, J. Loy, H. Greub, J.F. McDonald, "F-RISC/G: AlGaAs/GaAs HBT Standard Cell Library", Proc. IEEE ICCD, Oct 1991.

[PHIL93] R. Philhower, "Spartan RISC Architecture For Yield-Limited technologies", Ph.D. Thesis, Rensselaer Polytechnic Institute, 1993

[TYAGI93] A. Tyagi, "A Reduced-Area Scheme for Carry-Select Adders", IEEE Trans. on Computers EC-43. Vol. 42, no. 10, October 1993.

[WEST93] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd Edition, Addison-Wesley, Reading, Mass.,1993.

[WEIN91] A. Weinberger, "An adder design optimized for DCS logic", IBM Journal of Research and Development. Vol. 35 no. 3, May 1991.