An Update to the Optimized Carry Select Adder discussed in the
F-RISC Spring Semiannual Roprt
Since the writing of the Spring Semiannual Report, work has continued
on improving the optimized carry select adder. Recent results indicate
that our 500 ps is reachable, with critical path delays down
to 410 ps.
Three main courses were followed to inprove the performance of the adder:
Changing the interval to 2 bits per stage.
- Through SPICE analysis, it was determined that the original
estimate that the multiplexor delay equaled the gate delay was in
error. Typical delays turned out to be 30 ps per gate and 66 ps per
multiplexor. Approximating the ration of delays as 2 to 1 yields a new
stage size sequence of 5-7-9-11.
Increasing emitter follower and current trees to use 2.0 mA.
- Increasing the current through a current switch will decrease the
Isolating the carry and sum multiplexors with superbuffers.
- The longest paths through the adder all go through several of the
carry multiplexors. The carry signals which come out of the
multiplexors drive not only the next carry multiplexor but the sum
multiplexors as well. As each stage increases in size, the carry line
must drive more loads and longer interconnect as well. The carry
signals have been split in two: one line drives the carry multiplexor
and a superbuffer which drives the second line connected to all the
sum multiplexors for that stage. The line which connects one carry
multiplexor to the next will therefore only drive two loads at a time.
Improved Adder Data
Delays for important signals
|Input of least signiftcant bit|
|Output of most significant bit||a (Level 2)||b
(level 3)||cin (Level 2)|
|cout (Level 2)||371 ps||478 ps||228 ps|
|s (level 1)||402 ps||410 ps||260 ps |
SPICE Results from Improved Adder
Last Updated: 4/8/96