ABSTRACT

As integrated circuit device speeds continue to increase, the interconnections between devices are becoming a limiting factor in the overall circuit performance. To minimize the interconnect delay, special care must be taken during the physical design stage. This work examines several different aspects of physical design which have previously been ignored. The results have been applied to the development of a wideband 2.04 GHz - 13.66 GHz voltage-controlled oscillator, a 189.4 ps 32x8 register file and a 371.0 ps 32x16 cache ram block. These circuits have been developed in support of F-RISC/G, a 1 GHz fast-RISC processor developed at Rensselaer Polytechnic Institute.

To obtain maximum performance in the GHz regime, accurate extraction of parasitic capacitance is essential. Most extraction tools model the interconnections using planar layers although the actual fabricated structures may be highly non-planar. The error introduced when using planar models for non-planar structures is investigated and estimates for increased parasitic capacitance are generated using actual wiring statistics from F-RISC/G. The forced-feedthrough standard cell methodology used throughout the processor has been investigated in terms of area and found to be inefficient.

Techniques for matched-capacitance have been developed and applied to a very-wide-bandwidth voltage controlled oscillator. The circuit makes use of frequency multiplication and division to increase the output range. To reduce phase error, the frequency multiplier uses a novel, fully-symmetric exclusive-or circuit. The oscillator has a measured output range of 2.04 GHz to 13.66 GHz, the widest bandwidth reported for any voltage-controlled oscillator, either digital or analog.

A 189.4 ps register file with 32 rows of 8 bits apiece has been developed and incorporates a novel voltage-dividing memory cell. The circuit layout has been optimized to reduce the delay due to parasitic capacitance to 48.3 ps, or 34.2% of the intrinsic circuit delay. A lower-power 32x16 version of the circuit has been developed for use within a 4-kb cache ram chip. The circuit has a read access time of 371.0 ps and uses a novel circuit to reduce the recovery time after a write.