Appendix B

Register File Netlist and Schematics

rf : TS q1, SM q3, vary decoder total R
* ********************* 
* *** FINAL VERSION *** 
* ********************* 
* This version reduces some of the QuickCap capacitance values because the 
* Q1 metal is doubly estimated. 
* 200 ps register-file: 200.7 ps read (static address) 
* 180.6 ps read (dynamic address, 250 ps period) 
* 182.6 ps write 
* The parasitic capacitances in this file were generated using QuickCap 
* and the reduced ILD process file. The memory cell version is called 
* memcell_v4c. 
* bitline-bitline R=1k (rbit) 
* memcell Q1 AF=0.5 (memcellAF) 
* decoder Q1 AF=0.65 (decoderAF) 
* address line driver LCD pullups = 250 (raddriv) 
* address line decoder ratio = 200:250 (rtdecoder:rbdecoder) 
* senseamp bitline bias source resistor = 180 (rbitline) 
* Vth memory cell reference split-R = 425:325 (no parameters used) 
* memory cell cell common mode R = 190 (rshiftmc) 


* Address line driver 
.subckt addriv_h addr10 addr11 ad1b ad1 
* These values simulate the output interconnect resistance. 
rout1 addr10a addr10 1.25 
rout2 addr11a addr11 1.25 
* Capacitance is modelled on the top level. 
r1i134 addr10 addr11 4000 
q1ad11 $g_vcc n1n141 addr10a cc2q1 1 
q1ad12 $g_vcc n1n144 addr11a cc2q1 1 
*r1i131 n1n141 $g_vcc 220 
*r1i132 n1n144 $g_vcc 220 
r1i131 n1n141 $g_vcc {raddriv} 
r1i132 n1n144 $g_vcc {raddriv} 
c1i133 n1n141 n1n144 5ff 
q1ad13 $g_vcc ad1 n1n90 cc2q1 1 
q1ad16 $g_vcc ad1b n1n98 cc2q1 1 
q1ad14 n1n141 n1n90 n1n104 cc2q1 1 
q1ad15 n1n144 n1n98 n1n104 cc2q1 1 
q3a11 addr10 n1n90 n1n124 cc2q3 1.5 
q3a12 addr11 n1n98 n1n124 cc2q3 1.5 
qa18m11 n1n124 vrefadr1 n1n121 cc2q3 1.5 
qa3m12 n1n104 vrefadr1 n1n120 cc2q1 1 
qa3m13 n1n98 vrefadr1 n1n100 cc2q1 1 
q1a3m11 n1n90 vrefadr1 n1n136 cc2q1 1 
r1i127 $g_vee n1n121 25 
r1i128 $g_vee n1n136 150 
r1i147 $g_vee n1n100 150 
r1i148 $g_vee n1n120 125 
* Reference voltage generator 
r1i79 n1n114 $g_vcc 1400 
r1i80 n1n111 $g_vcc 1400 
r1i129 $g_vee n1n109 333 
r1i130 $g_vee n1n135 333 
qadref13 vrefadr1 vrefadr1 n1n135 cc2q1 0.5 
qadref12 n1n111 vrefadr1 n1n109 cc2q1 0.5 
qadref11 n1n114 n1n111 vrefadr1 cc2q1 0.5 
* Internal parasitic capacitances (isotropic, reduced ILD) from QuickCap 
ci0 ad1b 0 mcapacitance 28.6f 
ci1 ad1 0 mcapacitance 26.7f 
cii0 n1n98 0 mcapacitance 19.2f 
cii1 n1n90 0 mcapacitance 19.4f 
cbias vrefadr1 0 mcapacitance 96.8f 
cc1 n1n124 0 mcapacitance 43.5f 
cc2 n1n104 0 mcapacitance 28.7f 
cbc1 n1n111 0 mcapacitance 9.60f 
cbc2 n1n114 0 mcapacitance 2.54f 
co0 addr10a 0 mcapacitance 15.3f 
co1 addr11a 0 mcapacitance 16.4f 
cq1 n1n144 0 mcapacitance 7.73f 
* Original Q1445 device calls 
*q1a3m11 n1n90 vrefadr1 n1n136 q1445 1.5 
*q1ad11 $g_vcc n1n141 addr10 q1445 1.5 
*q1ad12 $g_vcc n1n144 addr11 q1445 1.5 
*q1ad13 $g_vcc ad1 n1n90 q1445 1.5 
*q1ad16 $g_vcc ad1b n1n98 q1445 1.5 
*q1ad14 n1n141 n1n90 n1n104 q1445 1.5 
*q1ad15 n1n144 n1n98 n1n104 q1445 1.5 
*qa3m12 n1n104 vrefadr1 n1n120 q1445 1.5 
*qa3m13 n1n98 vrefadr1 n1n100 q1445 1.5 


* Sense amplifier 
.subckt sense_h bitlinel bitliner dout0 dout0b 
* Output driver ckt. 
*r1i48 dout0b $g_vcc 85 
*r1i49 dout0 $g_vcc 85 
r1i48 dout0b $g_vcc {rsense} 
r1i49 dout0 $g_vcc {rsense} 
qsense0l dout0 bitlinel n1n39 cc2q1 1 
qsense0r dout0b bitliner n1n39 cc2q1 1 
*isensc0 n1n39 $g_vee 3ma Ideal source for output driver 
*rsensc0 n1n39 $g_vee 200 Original emitter R value 
rsensc0 n1n39 $g_vee 150 
* Bitline current sources 
qbitc0l bitlinel vrefsens n1n31 cc2q1 0.5 
qbitc0r bitliner vrefsens n1n32 cc2q1 0.5 
*rbitl $g_vee n1n31 180 
*rbitr $g_vee n1n32 180 
rbitl $g_vee n1n31 mrbitline {rbitline} 
rbitr $g_vee n1n32 mrbitline {rbitline} 
* Reference voltage generator 
r1410f1 n1n5 $g_vcc 1400 
r1410f2 n1n18 $g_vcc 1400 
r333p3f2 n1n30 $g_vee 333 
r333p3f1 $g_vee n1n29 333 
qvref1 n1n18 n1n5 vref1 cc2q1 0.5 
qvref2 vref1 vref1 n1n29 cc2q1 0.5 
qvref3 n1n5 vref1 n1n30 cc2q1 0.5 
vref vref1 vrefsens dc 0v 
fvref vref1 $g_vcc vref 7 
* Dummy loads 
c1i53 dout0b $g_vee mcapacitance 50ff 
c1i54 dout0 $g_vee mcapacitance 50ff 
r1i45 $g_vcc n1n22 312.5 
r1i46 $g_vcc n1n25 312.5 
r1i47 $g_vcc n1n41 312.5 
r1i59 $g_vcc n1n10 312.5 
i1i50 n1n26 $g_vee 0.8m 
i1i55 n1n24 $g_vee 0.8m 
qload0high n1n10 dout0 n1n26 cc2q1 0.5 
qload0bhigh n1n41 dout0b n1n26 cc2q1 0.5 
qload0low n1n22 dout0 n1n24 cc2q1 0.5 
qload0blow n1n25 dout0b n1n24 cc2q1 0.5 
* Nah's original values 
*r1i48 dout0b $g_vcc 100 
*r1i49 dout0 $g_vcc 100 
*r1410f1 n1n5 n1n60 1410 
*r1410f2 n1n18 n1n60 1410 
*rbitr $g_vee n1n32 150 
*rbitl $g_vee n1n31 150 
*rsensc0 n1n39 $g_vee 300 
*qsense0l dout0 bitlinel n1n39 cc2q1 0.5 
*qsense0r dout0b bitliner n1n39 cc2q1 0.5 
* bitline_r = bitliner 
* bitline_l = bitlinel 


* Memory cell dual-emitter device 
.subckt d2etrans b c d e1 e2 
d1i28 d c schott 
*q1i32 c b e1 cc2q1 0.5 
q1i32 c b e1 cc2q1 {memcellAF} 
q1i33 c b e2 cc2q1 0.5 


* Threshold voltage generator 
.subckt vth3n2 vth 
* Difference amplifier ckt. 
r1i121 inl n1n35 {rvthfeed} 
r1i122 n1n304 inr {rvthfeed} 
qvth9 n1n19 inr n1n161 cc2q1 0.5 
qvth10 inr inr n1n349 cc2q1 0.5 
qvth11 inr inr n1n349 cc2q1 0.5 
qvth12 n1n349 n1n466 n1n370 cc2q1 0.5 
r1i167 $g_vee n1n294 {rvthamp2} 
r1i168 $g_vee n1n286 {rvthamp1} 
*c1i65 n1n538 n1n304 {cvthfeed} 
*c1i66 n1n35 outamplb {cvthfeed} 
r1i87 n1n19 outamplb {rvthcol2} 
r1i88 n1n541 n1n19 {rvthcol1} 
r1i89 n1n85 n1n19 {rvthcol1} 
r1i90 n1n538 n1n19 {rvthcol2} 
r25a n1n67a n1n67 25 
r25b n1n67b n1n67 25 
qvth6 n1n538 n1n541 n1n67a cc2q1 1 
qvth7 outamplb n1n85 n1n67b cc2q1 1 
* R/W Logic matching ckt. 
qvthbig1 n1n19 n1n538 vth cc2q3 1.5 
rvthrwur inr vth mrrwcol {rrwcol} 
rvthrwul inr vth mrrwcol {rrwcol} 
rvthrw $g_vee n1n370 mrrwsc {rrwsc} 
q1p2ma1 n1n161 vref n1n365 cc2q1 0.5 
q3ma1 n1n69 vref n1n286 cc2q1 0.5 
q1p2ma2 n1n54 vref n1n188 cc2q1 0.5 
q2ma1 n1n67 vref n1n294 cc2q1 1 
vccvth $g_vcc n1n19 dc 0 
q1i518 n1n19 n1n538 vth cc2q3 1.5 
qvth5 n1n541 n1n35 n1n69 cc2q1 0.5 
qvth8 n1n85 n1n304 n1n69 cc2q1 0.5 
* Memory cell matching ckt. 
xqvth3 mcolll mcollr mtop n1n54 mbottom d2etrans 
xqvth1 mcollr mcolll mtop mcollr mbottom d2etrans 
r1i50a mbottom mbottom1 200 
r1i50 $g_vee mbottom1 3400 
r1i39 n1n44 n1n19 {8*(rtdecoder+rbdecoder)} 
qvth13 n1n19 n1n44 mtop cc2q1 1 
*rvthmcdr mcollr inl 325 
*rvthmcur inl mtop 425 
rvthmcl mtopa mcolll 750 
r1 mtop mtopa {rshiftmc} 
rvthmcur inl mtopa {rtmemcell} 
rvthmcdr mcollr inl {rbmemcell} 
r1i165 $g_vee n1n365 mrbitline {rbitline} 
r1i169 $g_vee n1n188 mrbitline {rbitline} 
* R/W logic bias ckt (matches Write buffer) 
r180a n1n19 n1n19a 180 
qvthref1 n1n19 n1n19a n1n461 cc2q1 0.5 
qvthref2 n1n461 n1n461 n1n466 cc2q1 0.5 
d1 n1n466 n1n466a schott 
*r1i467 $g_vee n1n466 800 
*r1i467 $g_vee n1n466 {rvthsrc} 
r1i467 n1n466a $g_vee {rvthsrc} 
* Reference voltage generator 
qvref1 n1n522 n1n164 vref cc2q1 0.5 
qvref2 vref vref n1n336 cc2q1 0.5 
qvref3 n1n164 vref n1n338 cc2q1 0.5 
r333p3f1 $g_vee n1n336 333 
r333fp3f2 n1n338 $g_vee 333 
r1410f2 n1n522 n1n19 1400 
r1410f1 n1n164 n1n19 1400 
* Nah's original values 
*r1i39 n1n44 n1n19 3200 
*qvth13 n1n19 n1n44 mtop cc2q1 0.5 
*rvthmcdr mcollr inl 300 
*rvthmcur inl mtop 450 
*r1i50 $g_vee mbottom 3400 
*r1i165 $g_vee n1n365 150 
*r1i169 $g_vee n1n188 150 
*qvth6 n1n538 n1n541 n1n67 cc2q1 0.5 
*qvth7 outamplb n1n85 n1n67 cc2q1 0.5 
*q2ma1 n1n67 vref n1n294 cc2q1 0.5 
*r1i467 $g_vee n1n466 2k 
*qvthref1 n1n19 n1n19 n1n461 cc2q1 0.5 
*r1410f2 n1n522 n1n19 1410 
*r1410f1 n1n164 n1n19 1410 


* Read/Write Logic 
.subckt rwlogic_h bitlinel bitliner d0 d1 wr wrb 
xvth vth vth3n2 
* Input level shifter 
q1datab3 $g_vcc d1 d1a cc2q1 0.5 
q1datab4 $g_vcc d0 d0a cc2q1 0.5 
rdin d1b $g_vee 3000 
rdinb d0b $g_vee 3000 
d1i52 d1a d1b schott 
d1i53 d0a d0b schott 
* Remainder of ckt. 
qbit0l $g_vcc bitl bitlinel cc2q1 0.5 
qbit0r $g_vcc bitr bitliner cc2q1 0.5 
qwrwin rwdin wr n1n15 cc2q1 0.5 
qwrwinb n1n12 wrb n1n15 cc2q1 0.5 
qwrdin bitl d1b rwdin cc2q1 0.5 
qwrdinb bitr d0b rwdin cc2q1 0.5 
qwrrr bitr bitr n1n12 cc2q1 0.5 
qwrrl bitl bitl n1n12 cc2q1 0.5 
rrwl bitl vthp mrrwcol {rrwcol} 
rrwr bitr vthp mrrwcol {rrwcol} 
rrws n1n15 $g_vee mrrwsc {rrwsc} 
* load multiplier, parasitic capacitances 
c1i32 vthp $g_vcc mcapacitance 80ff 
fvth1i33 vth $g_vee vsenvth 7 
vsenvth vth vthp 0v 
c1i64 n1n15 $g_vcc mcapacitance 14ff 
c1 bitl $g_vcc mcapacitance 9.6ff 
c2 bitr $g_vcc mcapacitance 9.6ff 
* bitline_r = bitliner 
* bitline_l = bitlinel 


* Memory cell 
.subckt memcell_h bitl bitr wordhigh 
r1 wordhigh word {rshiftmc} 
c1 wordhigh word {cshiftmc} 
r1i7 word q0 750 
r1i9 word q1 750 
x1i4 q0 q1 wordhigh bitr1 com d2etrans 
x1i6 q1 q0 wordhigh bitl1 com d2etrans 
vbitr bitr bitr1 0v 
vbitl bitl bitl1 0v 
r1i18 com wordlow 200 
*r1i10 $g_vee wordlow2 450 
r1i10 $g_vee wordlow2 425 
* Parasitic capacitances, load multipliers 
*c1i17 wordlow $g_vee 56ff 
c1i17 wordlow $g_vee mcapacitance 7.1ff 
c1i21 wordlow2 $g_vcc mcapacitance 57.3ff 
c1i21a wordlow2 $g_vcc mcapacitance 12ff 
c1i25 com $g_vcc mcapacitance 10ff 
*c1i27 q0 $g_vcc mcapacitance 10.5ff 
*c1i29 q1 $g_vcc mcapacitance 10.5ff 
*c1i29a q1 q0 mcapacitance 4.1ff 
c1i27 q0 $g_vcc mcapacitance {cq0q1} 
c1i29 q1 $g_vcc mcapacitance {cq0q1} 
c1i29a q1 q0 mcapacitance {cq0q1Miller} 
f1i19 $g_vcc wordlow3 vmcellc3 7 
vmcellc3 wordlow wordlow2 0v 
vword3 wordlow3 wordlow2 0v 
* This stuff is now located in the decoder subcircuit 
*c1i37 wordhigh $g_vee 86ff 
*c1i37 wordhigh $g_vee 12.2ff 
* collector_r = q1 
* collector_l = q0 
* bit_r = bitr 
* bit_l = bitl 


* Five Q1 address decoder w/ Area Factor parameter 
* The area factor should be 0.65 to handle 2.6mA of current 
* (1.2um X 2.6um emitter finger) 
.subckt trans5e b c e1 e2 e3 e4 e5 
q1 c b e1 cc2q1 {decoderAF} 
q0 c b e2 cc2q1 {decoderAF} 
q2 c b e3 cc2q1 {decoderAF} 
q3 c b e4 cc2q1 {decoderAF} 
q4 c b e5 cc2q1 {decoderAF} 


* Address decoder 
.subckt decoder_h e0 e1 e2 e3 e4 wordhigh 
rtodec $g_vcc decbase mrtdecoder {rtdecoder} 
rbodec decbase wordbase mrbdecoder {rbdecoder} 
q1i14 $g_vcc wordbase wordcol1 cc2q3 1.5 
q1i4 $g_vcc wordbase wordcol1 cc2q3 1.5 
xqdecod3 decbase wordbase e0 e1 e2 e3 e4 trans5e 
* Parasitic resistance, capacitance, load multipliers 
rout1 wordcol1 wordcol2 0.5 
c1 wordcol2 $g_vcc mcapacitance 85ff 
c2 wordcol2 $g_vcc mcapacitance 12ff 
f1i9 wordcol2 $g_vee vword3 7 
vword3 wordcol2 wordhigh 0v 
c1i23 wordbase decbase mcapacitance 4.5ff 
c1i34 wordbase $g_vcc mcapacitance 41ff 
c1i35 decbase $g_vcc mcapacitance 13.5ff 
* These are Nah's original values 
*rtodec $g_vcc decbase 200 
*rbodec decbase wordbase 200 
* These are Han's values 
*rtodec $g_vcc decbase 175 
*rbodec decbase wordbase 250 


* Write buffer 
.subckt writebuff in inb out outb 
q54 n1n6 in n1n14 cc2q1 0.5 
q55 n1n9 inb n1n14 cc2q1 0.5 
r64 n1n6 n1n92 180 
r65 n1n9 n1n92 180 
r59 o0 o1 500 
q53 o0 in n1n59 cc2q1 0.5 
q56 o1 inb n1n59 cc2q1 0.5 
r62 n1n59 $g_vee 500 
r63 n1n14 $g_vee 800 
*q57 n1n92 n1n9 o1 cc2q1 0.5 
*q58 n1n92 n1n6 o0 cc2q1 0.5 
q57 $g_vcc n1n9 o1 cc2q1 0.5 
q58 $g_vcc n1n6 o0 cc2q1 0.5 
q59 $g_vcc $g_vcc n1n92 cc2q1 0.5 
* Parasitic capacitances, load multipliers 
c1i108 out $g_vcc mcapacitance 81ff 
c1i109 outb $g_vcc mcapacitance 81ff 
c1i108a out $g_vcc mcapacitance 17ff 
c1i109a outb $g_vcc mcapacitance 17ff 
c1i110 inb $g_vcc mcapacitance 18ff 
c1i111 in $g_vcc mcapacitance 18ff 
c1i110a inb $g_vcc mcapacitance 4.5ff 
c1i111a in $g_vcc mcapacitance 4.5ff 
f1 o0 $g_vee vout0 7 
vout0 o0 outb 0v 
f2 o1 $g_vee vout1 7 
vout1 o1 out 0v 


* Input conditioning circuits - basicall level-shifting buffers 
.subckt l1buffer in0 in1 out0 out1 
q1 out0 in1 com cc2q1 
q2 out1 in0 com cc2q1 
*r1 com $g_vee 1.9k 
i1 com $g_vee 2ma 
rout0 out0 $g_vcc 125 
rout1 out1 $g_vcc 125 


.subckt l2buffer in0 in1 out0 out1 
q1 in0a in1 com cc2q1 
q2 in1a in0 com cc2q1 
*r1 com $g_vee 1.9k 
i1 com $g_vee 2ma 
rout0 in0a $g_vcc 125 
rout1 in1a $g_vcc 125 
q3 $g_vcc in0a out0 cc2q1 
q4 $g_vcc in1a out1 cc2q1 
r2 out0 $g_vee 1.9k 
r3 out1 $g_vee 1.9k 


.subckt l3buffer in0 in1 out0 out1 
q1 in0a in1 com cc2q1 
q2 in1a in0 com cc2q1 
*r1 com $g_vee 1.9k 
i1 com $g_vee 2ma 
rout0 in0a $g_vcc 125 
rout1 in1a $g_vcc 125 
q3 $g_vcc in0a in0b cc2q1 
q4 $g_vcc in1a in1b cc2q1 
q5 in0b in0b out0 cc2q1 
q6 in1b in1b out1 cc2q1 
r2 out0 $g_vee 1.9k 
r3 out1 $g_vee 1.9k 


* Parasitic capacitances & resistances 
*c1i98 bitr $g_vcc 80ff 
*c1i99 bitl $g_vcc 80ff 
*c1i41 bitl $g_vee 0.23pf 
*c1i42 bitr $g_vee 0.23pf 
*c1i43 bitliner $g_vcc 317ff 
*c1i44 bitlinel $g_vcc 317ff 
*ca adrv0n $g_vee 425ff 
*c0 adrv0bn $g_vee 425ff 
*c1i0 word0 $g_vcc mcapacitance 88ff 
*c1i1 word1 $g_vcc mcapacitance 88ff 
*c1i2 word2 $g_vcc mcapacitance 88ff 
*c1i3 word3 $g_vcc mcapacitance 88ff 
* 24ff reduction for Q1 collectors (1.47ff apiece)n 
c1i0 word0 $g_vcc mcapacitance 62ff 
c1i1 word1 $g_vcc mcapacitance 62ff 
c1i2 word2 $g_vcc mcapacitance 62ff 
c1i3 word3 $g_vcc mcapacitance 62ff 
*c1 adrv0n $g_vcc mcapacitance 340ff 
*c2 adrv0bn $g_vcc mcapacitance 340ff 
* 23ff reduction for Q1 emitters (1.47ff apiece) 
c1 adrv0n $g_vcc mcapacitance 317ff 
c2 adrv0bn $g_vcc mcapacitance 317ff 
c3 adrv0n adrv0bn mcapacitance 60.2ff 
c4 n1n1671 $g_vcc mcapacitance 340ff 
c5 n1n1669 $g_vcc mcapacitance 340ff 
c6 n1n1671 n1n1669 mcapacitance 60.2ff 
*c7 bitliner $g_vcc mcapacitance 0.23pf 
*c9 bitlinel $g_vcc mcapacitance 0.23pf 
*c7 bitliner $g_vcc mcapacitance 0.245pf 
*c9 bitlinel $g_vcc mcapacitance 0.245pf 
* 45ff reduction for Q1 emitters (1.47ff apiece) 
c7 bitliner $g_vcc mcapacitance 0.2pf 
c9 bitlinel $g_vcc mcapacitance 0.2pf 
c11 din0 $g_vcc mcapacitance 15ff 
c12 din1 $g_vcc mcapacitance 15ff 
* These simulate the bitline resistance. 
rbit1 bitliner bitr 25.5 
rbit2 bitlinel bitl 25.5 
*rbit1 bitliner bitr 22.5 metal-2 wires 
*rbit2 bitlinel bitl 22.5 
rbitline bitliner bitlinel {rbit}


* Load multipliers and sensors 
vleak1b n1n1551 adr1high 0v 
f1i1298 $g_vcc adr1high vleak1b 5.2 
e1i1348 addrhigh 0 adr1high 0 1 
veewrbuf n1n1806 $g_vee dc 0v 
f1i1838 $g_vcc adrv0bn vleak0b 4.2 
f1i1847 $g_vcc adr1low vleak1 5.2 
vleak1 n1n1854 adr1low 0v 
vmcellr n1n1785 bitliner 0v 
vmcelll n1n1783 bitlinel 0v 
f1i696 $g_vcc bitlinel vmcelll 28 
f1i697 $g_vcc bitliner vmcellr 28 
vleak0b adrv0bp adrv0bn 0v 
vleak0 adrv0p adrv0n 0v 
f1i852 $g_vcc adrv0n vleak0 4.2 
vccdbuf $g_vcc n1n1701 dc 0v


* Ideal sources 
vccl $g_vcc 0 0v 
veel $g_vee 0 -5.2v 
vlow n1n1671 0 -0.25v 
vhigh n1n1669 0 0v


* Data conditioning buffers 
xindata d0in d1in din0 din1 l1buffer 
xinaddress ad0in ad1in addr1 addr0 l1buffer 
xinwrite wr1in wr0in wr1 wr0 l3buffer 
*xdbuff dinsig dinbsig din0 din1 n1n1701 $g_vee databuff 
*xdbuff d0in d1in din0 din1 n1n1701 $g_vee databuff


* Subcell calls 
xwritebuf wr0 wr1 wrb0 wrb1 writebuff 
xaddriv14 adr1low adr1high n1n1671 n1n1669 addriv_h 
xaddriv0 adrv0n adrv0bn addr1 addr0 addriv_h 
xsenseamp bitlinel bitliner dout0 dout0b sense_h 
xrwlogic bitl bitr din0 din1 wrb1 wrb0 rwlogic_h 
xdecoder0 adrv0n n1n1551 addrhigh addrhigh addrhigh word0 decoder_h 
xdecoder1 addrhigh addrhigh addrhigh addrhigh adrv0bn word1 decoder_h 
xdecoder2 adrv0p addrhigh addrhigh addrhigh adrv0bp word2 decoder_h 
xdecoder3 addrhigh addrhigh addrhigh addrhigh n1n1854 word3 decoder_h 
xmemcell0 bitlinel bitliner word0 memcell_h 
xmemcell1 bitlinel bitliner word1 memcell_h 
xmemcell2 n1n1783 n1n1785 word2 memcell_h 
xmemcell3 bitlinel bitliner word3 memcell_h


* Model and parameter definitions 
* Models were used to perform Monte Carlo analyses & see if anything 
* interesting came up. Not much happened. 
.model mrrwcol res (r=1 dev/uniform 0% lot/uniform 20%) 
.model mrrwsc res (r=1 dev/uniform 0% lot/uniform 20%) 
.model mrbitline res (r=1 dev/uniform 0% lot/uniform 20%) 
.model mrtdecoder res (r=1 dev/uniform 0% lot/uniform 20%) 
.model mrbdecoder res (r=1 dev/uniform 0% lot/uniform 20%) 
.model mcapacitance cap (c={ccap} dev/uniform 0% lot/uniform 20%)


.param cvthfeed = 500ff 
.param rvthfeed = 4500 
.param rvthamp1 = 250 
.param rvthamp2 = 150 
.param rvthcol2 = 150 
.param rvthcol1 = 1000 
*Original values ; .param rtdecoder = 175, .param rbdecoder = 275 
.param rtdecoder = 200 
.param rbdecoder = {450-rtdecoder} 
.param rbitline = 180 
.param rrwcol = 450 
.param rrwsc = 400 
.param rbit = 1k 
*.param rtmemcell = 425 
.param rtmemcell = 350 
.param rbmemcell = {750-rtmemcell} 
.param memcellAF = 0.50 
.param decoderAF = 0.65 
.param rshiftmc = 190 
.param cshiftmc = 100ff 
.param raddriv = 250 
.param rsense = 85


* Resistor used to bias threshold gen. R/W logic current 
.param rvthsrc = 700 
* Mult. factor for all capacitances 
.param ccap 1 
* Memory cell q0/q1 total capacitance 
.param cq0q1 = 11.5ff 
* Memory cell q0/q1 Miller capacitance 
.param cq0q1Miller = 4.6ff


* Stimuli definitions 


*.step param rsense 80 170 30


.tran 1ps 3.5ns 2.0ns 10ps


vd1in d1in $g_vcc pwl ( 0 -0.25 1630ps -0.25 1650ps 0 2500ps 0 2520ps -0.25) 
vd0in d0in $g_vcc pwl ( 0 0v 1630ps 0v 1650ps -0.25v 2500ps -0.25v 2520ps 0v) 
vaddr0 ad0in $g_vcc pwl ( 0ps 0v 230ps 0v 250ps -0.25v 480ps -0.25v 500ps 
+ 0v 730ps 0v 750ps -0.25v 980ps -0.25v 1000ps 0v 2530ps 0v 2550ps 
+ -0.25v 2780ps -0.25v 2800ps 0v) 
vaddr1 ad1in $g_vcc pwl ( 0 -0.25v 230ps -0.25v 250ps 0v 480ps 0v 500ps 
+ -0.25v 730ps -0.25v 750ps 0v 980ps 0v 1000ps -0.25v 2530ps -0.25v 
+ 2550ps 0v 2780ps 0v 2800ps -0.25v) 
vwr1in wr1in $g_vcc pwl ( 0 -0.25v 1250ps -0.25v 1270ps 0v 1500ps 
*+ 0v 1520ps -0.25v 1930ps -0.25v 1950ps 0v 2180ps 0v 2200ps -0.25v 
+ 0v 1950ps 0v 2180ps 0v 2200ps -0.25v 
+ 3230ps -0.25v 3250ps 0v 3480ps 0v 3500ps -0.25v ) 
vwr0in wr0in $g_vcc pwl ( 0 0v 1250ps 0v 1270ps -0.25v 1500ps 
*+ -0.25v 1520ps 0v 1930ps 0v 1950ps -0.25v 2180ps -0.25v 2200ps 0v 
+ -0.25v 1950ps -0.25v 2180ps -0.25v 2200ps 0v 
+ 3230ps 0v 3250ps -0.25v 3480ps -0.25v 3500ps 0v )


.options itl1=200 itl2=120 itl4=25 itl5=10000 reltol=0.0001 tnom=27 chgtol=1e-17


.ic v(xmemcell0.q0)=-2.7 v(xmemcell0.q1)=-1.9 
+ v(xmemcell1.q0)=-1.9 v(xmemcell1.q1)=-2.7 
+ v(xmemcell2.q0)=-1.9 v(xmemcell2.q1)=-2.7 
+ v(xmemcell3.q0)=-1.9 v(xmemcell3.q1)=-2.7


* These were Nah's original parameter values


*.param rrwcol = 330 
*.step param rrwsc = 500 800 50 
*.param rbit = 300 
* He then tried these values 
*.param rrwcol = 450 
*.param cvthfeed = 500ff 
*.param rrwsc = 525 
*.param rvthfeed = 4500 
*.param rvthamp1 = 250 
*.param rvthamp2 = 170 
*.param rvthcol1 = 1000 
*.param rvthcol2 = 150


* These are the values Hans used in his schematics 


*.param rrwcol = 425 
*.param rvthcol1 = 800 
*.param rvthcol2 = 120 
*.param rvthamp1 = 200 
*.param rvthamp2 = 200 
*.param rvthfeed = 2500 
*.param rrwsc = 450 
*.param cvthfeed = 310ff


* v([bitliner]) v([bitlinel]) v([addr1]) v([addr0]) 
*+ v([xmemcell0.word]) v([xmemcell3.word]) v([word3]) 
*+ i(xsenseamp.rsensc0) v([xmemcell3.q0]) v([xmemcell3.q1]) 
*+ v([xrwlogic.vth]) v([xrwlogic.bitr]) v([xrwlogic.bitl]) 
*+ v([word0]) v([word1]) v([xmemcell0.q0]) v([xmemcell0.q1]) 
*+ v([wrb1]) v([wrb0]) v([dout0]) v([dout0b]) 
*+ v([adrv0n]) v([adrv0bn]) v([xrwlogic.xvth.mcollr]) 
*+ v([xsenseamp.n1n39]) v([wr1]) v([wr0]) 
*+ v([xmemcell0.word]) v([xmemcell1.word]) 
*+ i(xrwlogic.xvth.r1i87) i(xrwlogic.xvth.r1i90) i(xrwlogic.rrws) 
*+ i(xrwlogic.xvth.rvthrw) v([xrwlogic.bitr]) v([xrwlogic.bitl]) 
*+ ie(xdecoder0.xqdecod3.q1) ie(xdecoder1.xqdecod3.q4) 
*+ i(xsenseamp.rbitl) i(xsenseamp.rbitr) i(xmemcell0.vbitr) i(xmemcell0.vbitl) 
*+ i(rbitline) v([xrwlogic.xvth.inl]) v([xrwlogic.xvth.inr]) 
*+ i(xmemcell0.r1i18) i(xmemcell1.r1i18) v([xmemcell0.word]) 


.nodeset v(xmemcell0.q0)=-2.4v v(xmemcell0.q1)=-1.4 
+ v(xmemcell1.q0)=-2.8 v(xmemcell1.q1)=-2.4 
+ v(xmemcell2.q0)=-2.4 v(xmemcell2.q1)=-2.8


*.ic =v(mcoll1l)=-2.65 v(mcoll1r)=-2.5


* Model definitions 
The model definitions are proprietary information of Rockwell International and are not publicly disclosable under the Rockwell Non-disclosure Agreement (NDA).