Appendix C


RPI Testchip (HSCD) Results & Analysis

 

Overview

The RPI testchip has been included on two separate fabrication runs, the original 1992 run and the High-Speed Circuit Development (HSCD) run in 1994. The original run was plagued by yield problems, consequently only one data point was obtained at 500 ps. It is likely that the test circuitry rather than the register file limited the performance.

The testchip on the HSCD run had significantly better yield and was briefly tested when the chips were sent to Rensselaer in 1995. Other structures included on the HSCD run were tested and their performance was taken to indicate that the 30 GHz models were overly optimistic about performance while the switching models had better accuracy. Consequently, the register file on the testchip was not characterized (it also required additional probes which were difficult to set up).

Recently the HSCD run testchip was tested again, including the register file. The results have indicated that the register file runs significantly faster than predicted by the switching models. The most accurate model has been the 30 GHz model extrapolated from the S-parameter measurements. This Appendix describes the register file physical testing setup, experimental results and suggested modifications to the testchip for improved performance and testability.

Testchip Design Error

During testing, an error in the testchip design was discovered that prevented easy testing of the register file. The WRITE signal presented to the register file comes from a multiplexer (Figure C.1) which selects between an oscillating signal (based upon the on-chip VCO clock) and an external signal called External WRITE (EXT_WR). When the WRITE Select (WR_SEL) signal is sent high via the 6-channel probe, the oscillating signal is selected and data is written into the register file. When WR_SEL goes low, EXT_WR is selected and should stop the WRITE operation. Unfortunately, the EXT_WR pad was designed to rise high when not in use, hence the WRITE signal applied to the register file is always high unless the EXT_WR pad is forced low. A needle probe was used to force EXT_WR low and allow the testing of the register file but this error should be corrected in future versions of the testchip.

Figure C.1- Testchip register file WRITE select circuit

 

Physical Test Setup

The testchip was designed for use with a 6-channel 10-pin (2 ground, 2 power) microwave probe and a Ground-Power-Ground probe. Additional sites were provided to extend the functionality of the testchip, although not all are easily accessible with the two primary probes in place. Figure C.2 below identifies the probe locations. More information about the test circuitry, operation and probe settings may be found in [PHILH93].

Three probes are needed to test the register file on the testchip and a fourth is optional. A 6-channel probe at the Primary Probe Site provides two multiplexer select lines, the VCO control voltage, LFSR LOAD and the WRITE Select (WR_SEL) signals. One channel is reserved for the chip output and is used to observe the VCO, WRITE oscillator, LFSRs, and register file MATCH signals. The register file is powered up separately from the chip via the Register File Power site. The register file power is also used as a multiplexer select signal that chooses between the LFSRs and the comparison circuits.

The testchip was designed to only require probes at the Primary Probe Site and the Register File Power, however a design error (described earlier) has required the use of a third probe at the External WRITE (EXT_WR) site. A needle probe is required to pull the EXT_WR pad low (the default value is high) and allow the register file to enter READ mode. The pad site is actually designed for a Ground-Signal-Ground (GSG) probe but the large 6-channel probe at the Primary Probe Site may not allow enough room for the GSG probe, consequently a needle probe may be required.

Figure C.2 - Testchip probe locations for register file testing

Experimental Results

Register File Experimental Measurements Available

There are several different measurements that were obtained during testing, each of which is directly related to the register file performance. The voltage-controlled oscillator, or VCO, provides the on-chip clocking used for testing. The VCO provides clock signals for the two linear-feedback shift registers (LFSRs) which generate 31 5-bit pseudo-random patterns. One LFSR is used to provide addresses to the register file while the other provides the data that is stored in the register file and compared to the output of the register file. Although the LFSRs are clocked by the VCO, they do not necessarily operate over the full frequency range of the VCO (indeed, on the original testchip run both VCOs often did not function at the same frequencies, tremendously complicating testing). A pseudo-ring oscillator is also provided (called the WRITE oscillator) that provides unbiased information on the device and interconnection performance.

The most important measurement is the actual register file performance. A new address is applied to the register file on every rising clock edge (the data also changes on the rising clock edge). The output of the register file and the data LFSR pattern are fed into a XOR gate that compares the two values (see [PHILH93]). The comparator output is then fed into a master-slave latch which is clocked on the falling edge of the clock, hence the register file access time must be less than half of the clock period in order to be properly compared and latched. Each bit is individually compared and latched and is observable via the MATCH output signal, although only bits 0 and 7 are immediately available (the others require additional probes to set the multiplexers). As a final note regarding the test and clocking scheme, it is possible to directly observe the register file output but because the VCO period is typically larger than the desired READ access time, the performance cannot be verified this way.

Figure C.3 - Testchip register file output MATCH circuit

If the register file data matches the LFSR value and the access time (minus the comparator delay) is less than half the clock period, the comparator output will be 0. If all 31 bits being examined work properly, the MATCH output will be a flat line. Only 31 of the 32 rows are actually examined because the LFSRs cannot exit from the 00000 state, hence it is disallowed. If some bits in the register file are not functioning properly the MATCH output will be high only when those bits are examined (the LFSR value will not match the register file output).

In order to determine if the match circuitry is functioning properly, the data LFSR may be forced out of sync with the data written into the register file. The unsynchronized data between the LFSR and the register file results in mismatches and causes the comparator to go high. The comparator output for de-synchronized data has the same pattern as the LFSR.

VCO and LFSR Measurements

The VCO was measured for several chips across a range of control voltages. The LFSRs were examined to determine their maximum frequency. A plot of frequency vs. control voltage is shown for several VCOs in Figure C.4. The maximum frequencies for various VCOs and LFSRs are shown in Table C.1. The control voltages are not included because they are usually different for the maximum VCO / Address LFSR / Data LFSR values. The LFSR frequencies are the maximum VCO frequency at which the LFSR is fully functional. Missing LFSR values are due to either faulty circuitry or no measurement taken. Missing VCO values may be assumed to be at least equal to the LFSR frequencies.

 

Wafer # (Site #)

VCO (GHz)

Address LFSR (GHz)

Data LFSR (GHz)

VEE

6 (1,-1)

-

-

1.69

-5.2

6 (1,0)

2.37

2.37

1.68

-5.2

6 (1,1)

1.75

-

1.72

-5.2

6 (0,1)

1.65

-

-

5.2

 

2.25

1.68

1.68

-6.0

6 (0,0)

1.71

   

-5.2

 

2.22

-

2.41

-6.0

6 (0,-1)

2.32

-

1.30

-6.0

6 (-1,-1)

-

1.71

1.71

-6.0

6 (-1,0)

-

1.69

1.69

-6.0

6 (-1,1)

-

1.65

1.65

-6.0

3 (1,1)

-

2.37

1.68

-6.0

3 (1,0)

2.39

2.39

2.39

-6.0

3 (1,-1)

2.11

-

1.51

-6.0

3 (0,-1)

2.08

-

1.34

-6.0

3 (0,0)

2.28

2.26

2.08

-6.0

3 (0,1)

-

2.35

1.63

-6.0

3(-1,1)

-

2.31

1.59

-6.0

3 (-1,0)

-

2.31

1.67

-6.0

3 (-1,-1)

-

2.34

1.69

-6.0

8 (18) – lapped die

-

2.13

1.60

-6.0

Table C.1 - Maximum measured VCO, address and data LFSR frequencies from HSCD testchip

Figure C.4 - Testchip VCO frequency vs. control voltage experimental data

Write Oscillator Measurements

Experimental measurements of the WRITE oscillator frequency from the HSCD testchip are shown below in Table C.2. The WRITE oscillator was measured using the default pad setting, e.g. the longest path through the circuit.

Wafer # (Site #)

Frequency

VEE

6 (1,0)

1.04

-5.2

6 (0,0)

1.09

-6.0

6 (0,-1)

1.09

-6.0

3 (1,1)

1.09

-6.0

3 (1,0)

1.11

-6.0

3 (1,-1)

1.07

-6.0

3 (0,-1)

1.07

-6.0

3 (-1,-1)

1.07

-6.0

8 (18) – lapped die

0.99

-6.0

Table C.2 - Experimental WRITE oscillator frequency measurements

The WRITE oscillator circuit has been extracted and analyzed in SPICE using several device models (the anisotropic interconnect model was also used). The simulation data is shown in Table C.3. Comparing the experimental and simulation results indicates that the 2-sided switching model provides the best match. This is not surprising considering that the WRITE oscillator is a digital circuit, hence the 2-sided model is appropriate.

VEE (V)

50 GHz Rockwell (GHz)

30 GHz Extrapolated (GHz)

2-sided Switching (GHz)

-5.2

1.24

1.09

1.01

-5.4

1.26

1.10

1.03

-5.6

1.27

1.12

1.04

-5.8

1.28

1.13

1.05

-6.0

1.29

1.14

1.06

Table C.3 - Simulated performance of testchip WRITE oscillator

Register File READ Measurements

The proper operation of the register file is determined by examining the MATCH signal which compares the register file data with the LFSR data. When the LFSR data is stored in the register file and the WR_SEL signal is sent low (READ mode), the MATCH output should be a flat line. A flat line alone is not very interesting or significant, hence two other options are available for verifying that the RF is indeed working. First, the LOAD signal may be applied to de-synchronize (e.g. reload) the data LFSR, resulting in an offset between the data LFSR pattern and the register file data pattern. When these two patterns are compared using the XOR gate, the result is usually a pattern which has the same shape as the LFSR pattern. In short, after the data LFSR and register file data are de-synchronized by reloading the data LFSR, the MATCH output should resemble the LFSR pattern.

To determine the maximum speed at which the register file operates, the VCO frequency may be increased until the MATCH output begins to degrade. Remember that the address is applied to the register file on the rising edge of the VCO which the XOR comparator output is latched on the falling edge, hence the register file access time must be less than half of the VCO period. When the MATCH output is initially a flat line (e.g. the data LFSR and register file data match), increasing the VCO should eventually result in spikes appearing in the output signal, indicating that the data from the register file is not reaching the comparator in time to be compared and latched before the falling VCO clock edge. Similarly, if the data LFSR and register file data are de-synchronized by reloading the data LFSR, the register file access time may be determined by increasing the VCO frequency until the MATCH output pattern begins to degrade and drop some bits. A photograph of the mismatched signal is shown below in Figure C.5 at 222.7 ps or 4.49 GHz. This is the maximum mismatch signal frequency obtained from experimental measurements and is closely predicted using the 50 GHz (2 mA IC) device models from Rockwell. The frequency was increased slightly and the signal began to degrade as shown in Figure C.6 at 219.7 ps, or 4.55 GHz.

Figure C.5 - Testchip register file MATCH output with intentional mismatch at 4.49 GHz

Figure C.6 - Register file MATCH output on the verge of failure at 4.55 GHz