Chapter One



Simply stated, the physical goal of the F-RISC/G project is to design a processor with a 1 ns cycle time. This requires the integration of cutting-edge process and design technologies. In addition, methodologies and procedures that might have once been considered less important may become critical and should be reevaluated. This document examines both physical and topological optimizations to critical components of the F-RISC/G processor. In order to obtain high performance, the optimization process focuses primarily upon circuit speed with power dissipation and device count / chip yield as secondary considerations. The physical design is also examined, focusing upon specific situations which may be inefficient and degrade performance.


In the early 1980’s a new movement in computer architecture began with the development of reduced instruction set computers, commonly referred to as RISC machines [KATEV84, HENNE83]. The overall design philosophy was to keep the computer hardware as simple as possible but extremely fast. The instructions available were primitive by the standards of other established complex instruction set computers (called CISCs), but they included the majority of instructions used within an average program. To compensate for the reduced number of operations available, RISC processors have significantly improved throughput that allows them to perform more operations in the same amount of time.

Bipolar vs. CMOS

Because the RISC movement started during the advent of the silicon revolution, most RISC processors have been implemented in silicon using metal-oxide semiconductor field-effect devices, or MOSFETs for short. MOSFETs have been the predominant device in the industry due to their simple structure, low-cost fabrication and high integration levels. Although other technologies (most notably bipolar junction transistors, or BJTs) have better performance than MOSFETs, the development of complimentary MOS devices (CMOS) dramatically reduced circuit power consumption levels and provided a technological edge in terms of power vs. performance. However, this advantage may disappear as circuit speeds increase and the dynamic power dissipation of CMOS becomes comparable to other technologies with higher performance. With each new generation of CMOS, it becomes increasingly difficult to achieve significant performance gains through lithography or supply voltage scaling and, as a consequence, other device technologies become increasingly appealing.

In recent years bipolar devices have been overlooked for use in nearly all processors, primarily due to the false (but conventional) premise that bipolar circuits have higher power consumption. Because static CMOS circuits do not provide a direct path between power and ground, power is dissipated primarily when the circuit is switching and results in a dependence between power dissipation and frequency (Figure 1.1). In contrast, current-mode bipolar circuits have a constant flow of current (and hence higher static power dissipation) but the power dissipation does not increase significantly with frequency [DEYHI95].

Figure 1.1- Frequency-power relationship for bipolar and CMOS circuits

The static power dissipation of bipolar circuits has historically been large due primarily to the large feature sizes of the process. However, by improving the lithography and reducing the minimum dimensions, the static power consumption may be reduced without degrading the device performance. To obtain the maximum performance from a bipolar device, the current density in the emitter must be kept above a certain level otherwise the transistor gain drops off rapidly due to recombination in the base. With the relatively large feature sizes used in most bipolar processes, a significant amount of current is required to maintain sufficient current density for optimal performance (total current = current density X emitter area). However, if the emitter area is reduced, the total current may also be reduced without diminishing the current density and thus the overall speed remains about the same. In other words, by reducing the emitter area the total power consumption may be lowered without degrading the circuit speed. Figure 1.2 shows the relationship between the transition frequency fT and the collector current IC for several different emitter areas. As the emitter area is reduced, the total current IC (and thus the power) is also reduced while fT remains the same.

Figure 1.2 - Effect of reduced emitter area upon transition frequency fT and collector current IC

Currently, the feature sizes in most bipolar processes are one generation or more behind CMOS, hence there is significant room for improvement from leveraging existing interconnection processing technology. In contrast, improvements in CMOS processes are becoming considerably more difficult and expensive to achieve. As circuit frequencies continue to rise, the power dissipation of CMOS designs will continue to grow and may begin to rival bipolar circuits. With the improved performance and frequency-insensitive power dissipation of bipolar devices, the traditional power-performance advantage of CMOS will diminish if not completely evaporate. This becomes even truer when considering both the possibility of reduced power dissipation due to improved lithography and the performance improvement available from heterostructure bipolar transistors (HBTs). In short, at high frequencies bipolar circuits may run faster and consume less power than CMOS circuits.

F-RISC/G Historical Overview

In 1990, a new project was initiated a Rensselaer Polytechnic Institute to develop a 1 GHz RISC processor using HBTs in Gallium Arsenide (GaAs) that has more favorable performance properties but is more difficult to manufacture. The project goal was to determine if processors with significantly higher performance could be developed using low-yield, high-speed integrated circuit technologies. In keeping with the simple-is-faster philosophy, the processor was developed using RISC principles and gave rise to the project acronym "Fast RISC", or F-RISC for short.

To successfully harvest working systems from low-yield fabrication processes, two important design decisions were made: implementation of the processor using a multichip package and adoption of a "Spartan" RISC design. A multi-chip package allowed the use of smaller chips in the design rather than one large die. Because the device count per chip is kept low, the yields should be higher as compared to larger chips. One downside of this arrangement is the need for more interchip communications, increasing the complexity of the system timing and package design. As a result, the primary cache has been pipelined [MAIER96] to compensate for the interchip delays. The Spartan RISC design philosophy also keeps the amount of devices required to a bare minimum, thereby reducing the overall number of chips and improving yield.

The latest instantiation of F-RISC is called F-RISC/G and has been in development for six years. Since the critical components of the architecture have been designed prior to this work [PHILH93], there is little opportunity for large-scale architectural or chip-wide modifications. However, as we have become more familiar with the Rockwell process and device performance, many circuits have been fine-tuned to attain peak performance. To better understand the characteristics of the devices, numerous large and small test structures have been fabricated and tested. The results from these analyses have been incorporated back into the F-RISC/G design tools, allowing further optimization of the processor.


To achieve the high performance goals of the F-RISC/G processor, cutting edge device, circuit, and design technologies must be leveraged. Unfortunately, leading edge technologies have significant drawbacks that must be overcome, such as incomplete or inaccurate process models, low yield and high cost [ROCC90]. This section describes the device and circuit technology used in F-RISC/G.

GaAs/AlGaAs Heterojunction Bipolar Transistors

The F-RISC/G processor uses heterojunction bipolar transistors (HBTs) fabricated by Rockwell International (see Figure 1.3). The Rockwell process was chosen because it offered the best performance and yield available to the F-RISC/G group at the time. Heterostructure devices offer definite advantages over conventional homojunction technologies including significantly higher transconductance and unity-gain cutoff frequency (fT) due to increased emitter injection efficiency, lower intrinsic base resistance, and lower emitter-base capacitance [SZE81, ASBEC84, LONG90]. Compared to field-effect devices (FETs), bipolar devices have distinct advantages for circuit design such as uniform threshold voltage (VBE) and performance that is relatively independent of lithography [KROE82]. Similarly, GaAs has material properties that are more favorable than silicon, most notably higher electron mobility.

Figure 1.3 - Cross-section of Rockwell HBT (modified from [ASBEC84])


Emitter Size

1.4 mm x 3.0 mm

DC Current

2.0 mA


1.4 V


10.85 fF







t F

2.0 ps


30 GHz

Table 1.1 - Typical HBT device model parameters

Current-Mode Logic

The F-RISC/G processor uses differential current-mode logic (CML) circuit technology for a variety of reasons [NAH91, GREUB91]. Current-mode logic is inherently fast due primarily to current-steering and the avoidance of transistor saturation, has relatively few components and is simple to design [COOPE80]. The basis of CML is the current-switch that is composed of simply two transistors with a common emitter node.

Figure 1.4 - Differential current-switch circuit

Because the emitter nodes are connected, the operations of both devices are interrelated. Typically one of the base nodes (such as BASE1) is at a higher potential than the other (BASE2) and establishes the emitter voltage due to the built-in potential VBE across the base-emitter junction (VEMITTER=VBASE1-VBE). Because the other base is at a lower potential, the voltage drop across its base-emitter junction (VBASE2-VEMITTER) is less than VBE and consequently the device does not conduct current. If VBASE2 were to equal VBASE1, then the potential across the base-emitter junction for the second device would equal VBE and the device would conduct current. Likewise, if VBASE2 were to rise above the other base potential, then it would establish the emitter voltage and stop the first device from conducting current.

Single-Ended vs. Differential Signals

One essential characteristic of a CML circuit is the use of two related but varying voltages rather than one variable node and a fixed reference potential. Because the state of the current switch is dependent upon the relative difference between the two base potentials rather than their absolute voltages, CML is referred to as a differential circuit and the signals are called differential signals.

If one of the base nodes is connected to a fixed reference, the circuit is referred to as single-ended to indicate that there is only one variable input voltage. Single-ended circuits (such as emitter-coupled logic, or ECL) are also based upon the difference between the base potentials. However, because one potential is fixed, any noise injected onto the variable signal may be transferred directly to the output. This typically does not occur for circuits with differential inputs because the noise is injected onto both nodes, consequently the difference between the node potentials does not change and the noise does not affect the output. The ability to reject noise present on both inputs is called common-mode rejection and makes CML more suitable for a high-speed digital environment. Differential circuit technology has some other unique advantages over single-ended circuits such as the elimination of reference voltages and "free" inversions for digital logic (just switch the input signals) [PHILH93].

Stacked CML Gates

F-RISC/G CML circuits use standard -5.2V ECL power supply levels. A passive (i.e. resistive) source is used in order to allow three levels of current-switches to be stacked for greater logic flexibility (an example of a stacked three-level CML circuit is shown below in Figure 1.5). The voltage across the passive source is specified at 1 V rather than the 1.35 V required with an active source (due to the VBE drop across the active source). With the inherent high CMRR of differential logic, low logic swings are permissible and consequently the F-RISC/G system uses a swing of 250 mV (single-ended).

Figure 1.5 - Stacked current-mode logic gate

Disadvantages of CML

There are also some disadvantages to differential logic. Since both wires in a differential pair switch simultaneously, the change in potential is effectively twice the absolute voltage swing of the wires. For example, assume that D V is the difference in potential between two signals VBASE1 and VBASE2 in a differential pair. When viewed from the perspective of the VBASE1 signal, initially the VBASE1 signal is at +D V relative to the VBASE2 signal. After switching, VBASE1 is less than VBASE2 by D V, an effective change of 2D V. Because each wire experiences an effective voltage swing of twice the actual change, the capacitive coupling between the wires is also doubled.

Parasitic Coupling

The use of a semi-insulating substrate like GaAs also has advantages and disadvantages. Because the ground plane is so far away, the capacitance of a single node is generally reduced. On the other hand, because the ground plane is so far away, most coupling occurs between adjacent wires that can present serious problems for differential signals (see Figure 1.6 below).

Figure 1.6 - Comparison between parasitic coupling in GaAs and silicon

One solution is to route differential signals apart from each other to reduce the effective voltage swing, but this can present more serious problems with noise. Both wires in a differential pair should be routed side-by-side in order to ensure that any noise is injected onto both signals in a differential pair and is rejected due to the common-mode rejection property of CML. If wires are routed separately, the injected noise may not be identical and may not be rejected from the circuit output. Because every signal requires two interconnection traces, the routing of differential signals requires twice as much area and becomes more difficult. Until recently commercial routers have not been available that ensure the side-by-side routing of differential nets [NAH91], prompting the development of our own routing process that combines the two signals into one, routes the single combined signal and then splits it back into the differential components [LOY93].

Fabricated Designs and Experimental Results

During the development of the core processor chips, other circuits and structures have been fabricated, tested and analyzed in order to better understand the performance and characteristics of the Rockwell HBT process. To date there have been three distinct fabrication runs, each of which contained different circuits and structures. The first run contained a small test chip (appropriately called the "testchip") that was created at Rensselaer. The second fabrication run contained various circuits, interconnection test structures, and a high-speed circuit created exclusively to "push the envelope" and explore the higher-end capabilities of the Rockwell process. The most recent experimental data comes from one small structure placed on a reticle owned by another organization. This section describes each of these fab runs, the experimental results, the data analyses, and the extrapolated process models.

RPI Testchip (1991)

Before any of the F-RISC/G core architecture chips were designed, a "test" chip was developed in order to determine if the digital circuits would perform both functionally and at speed. The testchip would also provide valuable information regarding the accuracy of our CAD tools. In order to obtain as much information as possible for estimating the performance of the F-RISC/G processor, the testchip included critical components from the processor, namely a sub-200 ps register file, a comparator, and an 8-bit carry-select chain with two ripple-carry adders. The testchip contained 2600 HBTs, consumed 2.2 W, and measured 3.2 mm x 3.4 mm. The chips left the foundry at the end of May 1992 and were tested at Rensselaer starting in December 1992.

Testing revealed that the circuits were functionally correct but operated significantly slower than predicted [MCDON93, NAH94]. Unfortunately, poor yield severely restricted the number of testable circuits so relatively few data points were obtained. Because the testchip was designed to test critical parts of the F-RISC/G architecture, there were no dedicated process or device test structures included on the testchip. Any process control monitor (PCM) test structures placed on the wafer by Rockwell were destroyed when the chips were diced, hence we could not perform our own device and interconnection characterization. Although we didn’t have much data, we still attempted to develop more accurate device and interconnection models for the Rockwell process based upon the testchip results.

Testchip Device Modeling

The original Rockwell models had a baseline fT value of 50 GHz and were used in the development of the testchip. However, the experimental results indicated that the actual device performance was not as high as predicted, although the cause was not known. Rockwell did provide S-parameter measurements for one device that was fitted to a model based upon the Rockwell-supplied 50 GHz device model. S-parameter (or scattering parameter) measurements provide a description of the forward and reverse transmission characteristics of an object or network and are typically used for characterization in the high-frequency (e.g. microwave) regime. For an N-port object, the scattering parameters form an N x N matrix that describes the input-output relationship between any two ports.

Using the S-parameter measurements, the original device model provided by Rockwell was fitted to the experimental data and the fT value was calculated via simulation with SPICE. The new model demonstrated an fT value of approximately 30 GHz at a current level of IC=1 mA and VCE=5 V, significantly below the original model value of 50 GHz (the measured and simulated S21 parameters are shown in Figure 1.7). Clearly the original Rockwell model did not represent the measured device performance.

Figure 1.7 - Measured and simulated S21 (input-output transfer) parameters (from [MCDON93])

In 1995, Rockwell provided us with additional experimental data describing the relationship between fT, IC and VCE. The data verified that the device operated at 50 GHz (IC=2 mA, VCE=2 V) but also that the performance dropped when the collector current was reduced. Because the testchip circuits use about 1 mA on average, the original model overestimated the circuit performance while the 30 GHz model was more appropriate. However, even with the 30 GHz model the performance of the circuit was still slower than predicted by SPICE.

Other information received from the foundry indicated that the process had been "tweaked" to obtain better analog performance, specifically improved breakdown voltage but at the expense of the transistor gain b . The device gain was specified at b =100, however, the actual gain was on the order of 35 (the reduction in gain can be seen from the transfer coefficient value in the S-parameter plot). Experimental data from the testchip is shown below in Table 1.2.

Wafer #

VBE (mean, std. dev.)

b (mean, std. dev.)

BVCB0 (mean)


1.34 V, 0.6%

38.7, 29.9%

15.0 V


1.21 V, 32.7%

36.1, 64.5%

13.7 V


1.33 V, 1.1%

34.2, 36.1%

15.0 V


1.35 V, 0.8%

34.0, 35.0%

15.0 V

Table 1.2 - DC parametric test data from 1992 testchip fabrication run [MCDON93].

Testchip Interconnection Modeling

While the S-parameter device model did provide a better fit to the experimental results, it did not account for all of the degraded performance. Part of the problem was the unexpected inclusion of a thin layer of SiN above the first level of metallization. Rockwell did not provide experimental interconnection data so the modified process was modeled using the MagicCad interconnection simulation utilities and an early version of the QuickCap parasitic capacitance extractor. The simulation results indicated an increase in wire coupling of up to 50%. It was later determined that the interconnection dielectric heights were significantly thinner than specified by the foundry process description (see section 1.4.2 for more information regarding the thinner dielectrics).

Rockwell has also indicated that the polyimide may not be fully cured during the fabrication process in order to keep the processing temperatures low. Consequently, the incompletely-cured polyimide may exhibit a higher dielectric constant due to both water in the material (a by-product of the conversion process from polyamic acid to polyimide) and the less rigid polymer structure. Water is a by-product of the conversion process from polyamic acid to polyimide and is driven off during the curing process. The dielectric constant of polyimide can be affected by changes in humidity and may produce linear increases in the dielectric constant from 3.1 to 4.1 as the humidity goes from 0% to 100%, although some polyimides have reduced sensitivity to moisture [WONG93]. Even with fully-cured polyimide, moisture can still become a problem due to the hygroscopic nature of the material, hence further annealing procedures may be required after each processing step. Rigidity within the polymer chains also is important because the structures respond to electrical stimulus and consequently increase the dielectric constant. In fact, the low dielectric constant of polyimides are due to their rigid-rod-like backbone structure that reduces the electrical response. Other polyimide variations, such as fluorinated polyimide and benzocyclobutene (BCB), have also been developed that are less polar and consequently have lower response to electrical stimulus.

Regardless of the actual dielectric characteristics, the original parasitic capacitance numbers themselves contained significant error due to the use of design tools that estimated capacitance based upon the interconnection length. The capacitance per unit length was generated using 2-D models and then multiplied by the conductor lengths to obtain an estimate for the net capacitance. The opportunity for error in the extracted values was recognized early on, hence a worst-case model was developed that would be overly-pessimistic. Unfortunately, this pessimistic safeguard was bypassed due to the poorly characterized process model, consequently the estimated capacitance values were underestimated quite often. The accuracy of the capacitance extraction method has since been improved significantly using better interconnection models and three-dimensional tools that analyze each structure individually [QUICK96, LECOZ94, METAL91].

Testchip Voltage-Controlled Oscillator

The circuit with the highest yield on the testchip was the voltage-controlled oscillator (VCO) that was supposed to provide an on-chip clock at frequencies between 1.4 and 4.6 GHz. Experimental and simulated results for the VCO are shown in Figure 1.8 and Appendix C. The VCO and nearly every other circuit on the testchip was created using standard cells, hence there is a sizable amount of interconnection between the cells (see Figure 1.9). This mixture of interconnection and devices makes it difficult to simultaneously fit both device and interconnection simulation models to the results.

Figure 1.8 - Testchip VCO results (simulated and experimental)


Figure 1.9 - Layout of testchip voltage-controlled oscillator

In part because the results were so difficult to interpret, ARPA initiated the High Speed Circuit Development (HSCD) project to provide better characterization of the Rockwell process and facilitate the development of improved design tools. The F-RISC group was included as a subcontractor on the project to develop numerous test structures for characterizing the interconnection and devices and backannotation into simulation models.

High-Speed CAD Development (1994)

After the difficulty in modeling interconnection and device performance on the testchip, a number of unique individual test structures were created that would provide isolated information on different aspects of performance [GARG96]. These structures were included on a reticle provided under the HSCD initiative. The structures were fabricated in mid-1994 and tested in early 1995.

As with the testchip, the HSCD experimental results indicated that there was a significant difference between the process specifications and the fabricated chips. The dielectric spacing was found to be up to 50% of the specified thickness, but more importantly it varied depending upon the physical topology. Polyimide is believed to be planar until the curing process, at which time perfect planarization is lost to shrinkage because the film can no longer flow quickly enough to keep up with the drying process []. Planarization is also affected by the underlying topology, providing better results for closely-spaced structures than for solitary wires. Rockwell has performed a SEM cross-section analysis of the metal-1 / metal-2 dielectric spacing and found it to be 0.9 mm [LEE95], significantly less than the specified 1.6 mm. Researchers at the Mayo Foundation have also confirmed the reduced polyimide thickness [DEGER96].

Anisotropic Dielectric Characteristics

From finger-capacitor test structures another potentially serious interconnection problem was uncovered. In [EDELS95], the authors discussed the dielectric properties of polyimide and cited evidence of anisotropic effects in which the in-plane (e.g. horizontal) dielectric constant is up to 25% greater than the out-of-plane (e.g. vertical) value. Because nearly all of the coupling in a finger-capacitor structure is horizontal, the higher in-plane dielectric was more apparent and was estimated to be 25% higher. Anisotropic dielectrics can present a very serious problem especially for GaAs circuits, mainly because most of the capacitance is between horizontally adjacent wires. This problem is even worse for differential logic because both wires in a differential pair switch simultaneously, effectively doubling the voltage swing and thus the mutual capacitance between the wires.

Wide-bandwidth Voltage-controlled Oscillator (1994)

In order to probe the upper frequency range of the Rockwell process, an aggressive voltage-controlled oscillator was designed and included on the HSCD reticle. The goal was to create a custom layout that focused entirely upon performance in order to "push the envelope" and provide insight into the Rockwell HBT process. Specialized layout techniques were developed [CAMP195] that assisted the designer in creating a physical layout with a high-degree of capacitance matching between the nodes in a differential signal. The VCO architecture also incorporates high-speed quadrature frequency multipliers and dividers to increase the bandwidth of the circuit. The VCO was designed to operate at frequencies up to 20 GHz but the experimental results peaked at 13.66 GHz (the VCO is described in Chapter 2).

Latest Fabrication Run (1995)

The latest fabrication data was obtained from a ring-oscillator placed on a reticle provided by Dr. K.C. Wang of Rockwell International. In an attempt to retrieve some of the lost performance, two new device layouts were created based upon experimental designs from Rockwell.

In order to compensate for the degraded performance, it was proposed to scale the emitter area down by 33% and reduce the base-emitter junction capacitance. One concern about reducing the emitter area without a corresponding shrink in current was the consequent increase in current density beyond the specified process limit of 0.5 mA/mm2. This could result in dopant redistribution within the base that would adversely affect the device performance and stability. Discussions with Rockwell, however, indicated that the process could safely accommodate higher current densities up to 1.0 mA/mm2. As a result, the decision was made to shrink the emitter area even further to 50% in an attempt to overcompensate for the lost performance and any other (unknown) negative side effects of the shrunken device. One of the devices was given a third active base edge facing the emitter in order to reduce the external base resistance and increase the fT performance metric.

After the shrunken device was designed, it was placed in a 50-stage ring oscillator (Figure 1.10). Because the area for the test circuit was donated, the layout area was kept small and consequently the stages were lightly loaded. With the support of Dr. Wang, the circuit was tested at Rockwell and demonstrated a period of 1910 ps, approximately 21% slower than the 1492 ps predicted by the original Rockwell device model. While this was a significant improvement over the speed degradation predicted for the original device (1981 ps period using the 30 GHz device model, or 25% slower than expected), it was not a "magic bullet" that would recover all of the lost performance. It is surmised that the reduction in junction capacitance may have been offset by increases in both the base resistance (due to the reduced emitter periphery) and collector capacitance.

Figure 1.10 - Ring-oscillator with experimental transistor layout

To represent the performance of the ring oscillator, a new model was developed and called the 2-sided-base switching model. Another model, called the 3-sided-base switching model, was derived from the 2-sided model and demonstrates the performance if a third active edge was added to the base to reduce the intrinsic resistance Rb. In addition to the K.C. Wang ring oscillator, data from the HSCD circuits was also used in fitting the model. Both switching models have significantly lower performance than the extracted 30 GHz and original 50 GHz models. The 2-sided model was used along with the anisotropic internconnection model to predict the speed of the ring oscillator to within 0.5 %. Experimental measurements from circuits on the HSCD fabrication run were also verified to within a few percent [GREUB96].


Device Model

Area Factor

Simulated Delay (ps)

Measured Delay (ps)

K.C. Wang Ring Oscillator





VCO Ring Oscillator (IC=2 mA)





HSCD Ring Oscillator (IC=2 mA)





Long carry-chain





Table 1.3 - Comparisonof experimental and simulation data using 2-sided-base switching model [GREUB96]

Comments on Device Models

The data in Table 1.3 indicates that the 2-sided switching model is indeed accurate for predicting the speed of the ring oscillator circuits, however the 30 GHz and 50 GHz models are also based upon experimental data and are accurate under certain conditions. Why is there such a disparity between the switching and non-switching models?

To understand this disparity, consider the experimental basis for each model. The 30 GHz and 50 GHz models were derived from S-parameter measurements in which the device is forward-biased and always has some current flowing. Furthermore, the models were adjusted to better represent the high-current characteristics of the device required for many analog applications. In contrast, the switching models were based upon data from a digital ring-oscillator in which the currents are significantly lower. Because the devices in a digital CML circuit switch completely "on" and "off", each device must pass through a region of low current. Since the non-switching models are optimized for high-current levels, they are less accurate at low-current levels and underestimate the circuit delay.

Currently there are five distinct single-emitter device models available: the original 50 GHz Rockwell model, an updated (1996) 50 GHz Rockwell model, the 30 GHz model, and the 2-sided base and 3-sided-base switching models. Each model is accurate under certain conditions but the proper choice of models may cause confusion during the design process. In general, the 2-sided-base model is applicable to nearly all circuits in F-RISC/G, however, recent experimental results from the HSCD testchip have indicated that the switching models may not be appropriate for the analog memory circuits (it should be noted that digital circuits on the testchip have been verified using the 2-sided-base switching model). The testchip register file has been verified at 222.7 ps, significantly below the value predicted by the switching models but close to the non-switching model predictions (Chapter 3 and Appendix C). Unfortunately this information has been obtained after the redesign process (using the 2-sided-base switching model) was completed. On the other hand, the actual circuit performance should be better than originally expected (with the switching models) and thus provide a significant margin of safety.


Figure 1.11 - Milestones in the F-RISC/G project

Contributions to the Field

This work contains several contributions to the fields of high-speed circuit design and the physical layout of integrated circuits.

Development of Ultra-high Speed Memories

Design of an Ultra-Wide-Bandwidth, High-Speed Voltage-Controlled Oscillator

Physical Layout Design