Chapter Six


Capacitance Modeling for Non-planar
Interconnection Processes

 

As with most designs, the circuit and layout analysis relies in some way (either directly or indirectly) upon capacitance values which were generated using CAD tools rather than experimental measurements. Although the best CAD tools available may be used, there are still opportunities for error to be injected into the results. In this chapter, the modeling of capacitance is investigated and focuses specifically upon the effect of non-planarzed interconnections, called the "draping effect". Simple structures are analyzed with numerical capacitance extraction tools and compared to analytical results. From these simple structures, a more complex model is developed for a two-dimensional non-planar crossover structure and characterized. Finally, a three-dimensional non-planar crossover is examined and characterized in terms of height, width, separation and degree of non-planarity.

Introduction

One of the most critical aspects of high speed design today is the accurate extraction of circuit parasitics. As circuit speeds increase, the margin for error diminishes and any uncertainty in device or circuit parameters may degrade the performance of actual fabricated chips [ZHANG96]. For integrated circuits, parasitic capacitance is one of the most severe physical constraints upon circuit performance and consequently high quality capacitance extraction tools are a necessity. Good tools alone are not the only criteria necessary to generate accurate parasitic estimates. Accurate models for the physical processes are also needed, otherwise the discrepancy between the modeled structure and the fabricated circuits can become a source of error.

This chapter investigates the "draping effect" that results from non-planarized interconnections and focuses upon the generation of accurate parasitic capacitance values. The differences between the simplified planar models and the actual non-planar fabricated interconnection structures are examined. An analysis is performed which compares extracted two dimensional capacitance values with analytic solutions for simple structures. A discrete element model is created to represent a two-dimensional non-planar crossover and is used to investigate the effects of non-planarity upon interconnection parasitics. Finally, realistic crossover structures are created and analyzed in three dimensions to quantify the effect of non-planarized interconnection upon parasitic capacitance values.

Capacitance Extraction Methods

There are many methods available for calculating capacitance, most of which use the finite-element mesh (FEM) approach. By repeatedly solving Laplace’s equation, the electric field everywhere in the simulation region may be determined. Unfortunately, despite their high-accuracy, FEM tools tend to be slow due to the large number of iterations required for convergence, the sheer volume of the data structure, and the manipulation of the matrix. Other methods, such as the random-walk algorithm, have been developed which produce results at a much faster rate but possibly with less accuracy.

Analytical Methods

For simple geometries, it is possible to work out analytical expressions for conductor capacitance. From the conductor geometry and a set of boundary conditions, Laplace’s equation may be solved in order to obtain the capacitance. Unfortunately, analytical approaches quickly fall apart when more complex structures are introduced. One common method for dealing with the complexity of a structure is to use a conformal mapping which transforms the complex geometry into one which is simpler to analyze. This technique is used often for theoretical analysis but does not lend itself to use with the complex geometries typical found in most designs.

A commonly used alternative method is to select one or more wiring situations which could be analyzed analytically and then map the results onto real conductor geometries in a design. The disadvantage of this method is that the capacitance may or may not have significant amounts of error due to the mapping between the actual and idealized structures. In a design environment, underestimated capacitance can be devastating, consequently worst-case geometries are often used to develop the analytical models in order to provide pessimistic capacitance values. An improved estimate may then be obtained by selecting a model from a library of different geometries that may represent the actual structure more closely. Despite the level of sophistication present within the CAD tool, these methods may not provide the level of accuracy required for cutting-edge design. While pessimistic models avoid underestimating capacitance, they can also prevent a design from reaching its full potential.

Finite Element Methods

The most common numerical method for numerical capacitance extraction is the Finite Element Method, or FEM. This method is based upon the solution of Laplace’s equation throughout the region using a number of finite elements (typically arranged as a mesh) to calculate the electric field everywhere. Because the elements must be present everywhere within the region of analysis, large matrices are required. The element values are calculated based upon the boundary conditions and are iteratively recalculated until they are within a specified degree of error.

In some situations, FEM tools may have a higher-degree of accuracy than their analytical counterparts due to the fact that they can analyze actual geometries rather than approximate them. Unfortunately, these methods also can consume tremendous amounts of computing power and resources due to the sheer volume of the mesh. With such a large data structure, the amount of time and memory required to store and manipulate the information can outweigh the actual amount of computing being performed. While there are techniques available that can vary the density of the mesh, for a 3-dimensional region the memory and CPU time requirements can easily become impractical. As an example, the analysis of half of a F-RISC/G memory cell using METAL, a popular 3-D FEM tool [METAL91], was estimated by the program to require hundreds of megabytes of disk space and 20+ hours of CPU time. These amounts of resources are clearly impractical in light of the total analysis requirements for the F-RISC/G project.

Random-Walk Simulators

One alternative to 3-D FEM tools is a random-walk simulator [QUICK96]. Rather than determining the electric field everywhere in a system, a random-walk simulator follows a random path from one conductor to another. The path continues until another conductor or a system boundary has been contacted, at which point the capacitance for this particular path is added to the capacitance matrix. As the number of random walks increases, the statistical certainty of the total capacitance increases.

The random-walk method has the advantage of fast operation and much smaller data structures. A random-walk simulator can obtain a low-accuracy (~5-10%) result very quickly, however, to improve the accuracy of the result, the simulator must generate an exponentially-increasing number of walks. The F-RISC/G project was provided with the QuickCap random-walk capacitance extraction tool and has used it extensively for design, layout and analysis. It has proven to be indispensable both in relating experimental results to physical interconnection models and in the design and layout of time-critical circuits. For comparison purposes, the same analysis which would have required huge amounts of resources with the METAL program can be performed in under an hour using the QuickCap random-walk capacitance extraction tool and require less than a few megabytes of disk space.

Physical Modeling of Interconnect

All practical 3-dimensional simulators provide some method for importing layout information into the system for analysis. Because most layouts are represented using a 2-dimensional coordinate system along with layer information, the import procedure must convert the layout into a full 3-D representation based upon some physical model. Depending upon the model used and the actual interconnection fabrication process, this presents a possible source of error for the capacitance extraction.

The simplest method for creating a model of interconnection traces is to map each layer onto specific vertical coordinates with no consideration of structures underneath the layer, i.e. treating the layer as a plane which does not conform to the underlying surface (a planar model). Because the fabricated layers may exhibit a "draping effect" in which the layer conforms to the underlying surface topology, the planar interconnection model can differ from the fabricated structures and introduce error into the analysis. It is possible to create a structure which more accurately represents the conformal nature of the actual interconnections, however, this also requires significantly more time and information to generate. Of course, if the actual fabrication process is planar then the simple mapping technique may indeed be accurate. Unfortunately, as shown in the next section, the Rockwell process is not planar.

Figure 6.1 - Planar and non-planar conductor representations

Interconnection Fabrication Technology

Multilevel interconnections are fabricated basically by alternately depositing layers of metal and dielectric. As each layer of metal is etched to create individual traces of wire, the original planar surface becomes increasingly bumpy. Eventually, the non-planar surface becomes a limiting factor in the number of interconnection layers possible, due in part to the limited depth-of-focus of higher numerical aperture lenses [CAMPB96]. In addition, non-planar topographies may exhibit "a substantial capacitance increase (e.g., >20%)" when compared to flat geometries [EDELS95] (note that this work was related to silicon processes that have a nearby groundplane and significantly higher dielectric constants). To compensate, planarization technologies such as back-sputtering, reactive-ion etching etch-back, and chemical-mechanical polishing (CMP) have been developed [MURAK93] and are becoming widely used. These technologies will be necessary to meet future interconnection requirements of 10 or more layers [BOHR96].

Although the polyimide dielectric in the Rockwell HBT process does provide some degree of planarization, the overall process is not planar. This can be seen in the microphotograph of the voltage-controlled oscillator shown in Figure 6.2. Wide power rails are routed over wiring channels that are minimally spaced based upon the process design rules. The shadows that appear at the intersection of the wiring channels and wide power rails indicate that the upper metal layer does dip down somewhat between the wires in the channel. Unfortunately, the actual degree of planarization cannot be determined from the photograph and must be examined using scanning-electron microscope techniques.

Figure 6.2 - Non-planar features in VCO chip photograph

Effect upon Resistance and Capacitance

The simpler, planar representation of the metallization may be less-accurate than the non-planar version for several reasons. Resistance is typically modeled as the wire length multiplied by a sheet resistance factor. The wire length is defined in terms of squares, where the edge length of a square is simply the wire width. The only exception to this measurement procedure is for bends in the wire. For Manhattan geometries, each bend contributes of a square to the overall length of a wire. Depending upon the amount of conformality involved, the wire may or may not have increased resistance due to the additional bends when compared to a planar structure. Because the vertical bends in the wire have less resistance than a straight segment, any contribution they make to the overall wire length may cancel out and produce the same amount of resistance as a completely straight wire.

Capacitance is much more difficult to calculate, especially for more complex systems and structures. In a planar representation, all wires on the same metallization level will be placed on the same plane during the capacitance analysis. Assuming that the dielectric is somewhat conformal as well, this can result in either overestimated or underestimated crossover capacitance. As an example, consider the planar and non-planar conductor representations in Figure 6.3. It can be seen that the metal-1 and metal-2 separation is the same in both representations, at least for wires routed on top of each other. However, the metal-1 to metal-3 spacing is sharply reduced for the conformal structure that should then result in increased coupling.

Figure 6.3 - Detail of non-planar and planar conductor representations

Model Definition of Physical Dimensions

The surface planarity is usually described in terms of the degree of planarization p as

Eq. 12

where A is the height of the underlying step and B is the peak-to-trough distance of the coating (see Figure 6.4).

Figure 6.4 - Planarization definitions

In Figure 6.4, the dielectric height H is defined as the vertical spacing between two conductors (not including the thickness of the conductor) while the "conformality factor" D H (B) is the reduction in vertical spacing for adjacent unstacked conductors (e.g. conductors within the trough).

(a) Planar Model (b) Non-planar Model

Figure 6.5 - Parameters defining separation between conductors

Based upon the model shown in Figure 6.5, the relationship between conformality factor, dielectric height and horizontal offset may be explored. Plots for horizontal spacings of 2.0, 4.0 and 6.0 mm are shown in Figure 6.6, Figure 6.7, and Figure 6.8 respectively. The plots depict the percentage change in conductor separation as the horizontal offset (Y) and percent conformality (the conformality factor divided by dielectric spacing, or D H/H) are varied. A percent-conformality value of 0% corresponds to the planar interconnection model.

Figure 6.6 - Change in conductor spacings for dielectric spacing of 2.0 m m

 

Figure 6.7 - Change in conductor distance for dielectric spacing of 4.0 m m.

 

Figure 6.8 - Change in conductor distance for dielectric spacing of 6.0 m m.

The plots show that the percent-conformality of the dielectric (the dielectric peak-to-trough distance relative to the height) can have a significant impact upon the conductor spacing, thus indicating that conformal models may indeed have significantly higher capacitance. In order to establish the actual effect of the increase in capacitance, a series of analyses were undertaken using non-planar models.

Capacitance Model Development and Analysis

In order to develop a better understanding of the relationship between the interconnection structure and capacitance, a series of characterizations were performed which attempted to correlate simulation results with analytical models. The structures used in the analysis ranged from single conductors to three-dimensional non-planar wire crossovers. All simulations were performed using the QuickCap 3-D capacitance extraction tool but most structures were designed to represent two-dimensional models in order to simplify the analytical expressions.

Analytical Capacitance Models

Because it is important to understand the basic mechanisms and relationships before progressing to more complicated structures, a number of variations of a simple single-conductor model were analyzed. The basic model, shown in Figure 6.9, is a conductor suspended above a groundplane within a uniform dielectric material. The height, width and length parameters were varied over a wide range and the results compared to both parallel-place and microstrip transmission line capacitance equations.

Figure 6.9 - Basic single-conductor model

The capacitance of two parallel plates is given by

Eq. 13

where L is the plate length, W is the width, H is the separation and e is the permittivity of the dielectric. Because this equation neglects the fringing fields present at the plate edges, the accuracy of the result is dependent upon both the ratio of plate-area-to-height and plate-perimeter-to-area. For minimal fringing, the perimeter-to-area ratio must be minimized, consequently a square is the best solution.

Although it is simple and fairly accurate under certain restrictions, the parallel plate model is not sufficient for most structures. Improved accuracy in the capacitance estimate may be obtained by using more complicated analytic expressions. When the width of the conductor becomes narrower relative to its length, the structure begins to resemble a microstrip transmission line. As shown in Figure 6.10, a microstrip is basically a wire separated from a groundplane by a dielectric material. Because the wire is relatively narrow and the separation is large, fringing field lines from the top of the conductor may contribute significantly to the overall capacitance (the height of the wire is usually considered to be very thin in order to neglect fringing from the sides). The analysis of a microstrip is usually hampered by the presence of two dielectrics, namely the air above the microstrip (e air) and the dielectric separating the wire from the groundplane (e dielectric). For this analysis, it is assumed that the dielectric is uniform with the conductor encased within the interlevel dielectric material.

Figure 6.10 - Microstrip transmission line model

Because the height H of the wire above the groundplane is typically equal to (or larger than) the wire width and because the wire perimeter-to-area ratio is not close to optimal, the capacitance cannot be accurately represented using the parallel plate model. Instead, a more detailed expression may be derived based upon the solution of Laplace’s equation with specific boundary conditions. The capacitance of a microstrip may then be approximately given by

Eq. 14

where W is the width of the microstrip, H is the distance between the microstrip and the groundplane, and a is the distance between the conductor and the side walls [POZAR90]. This equation is an approximate solution for the microstrip structure shown Figure 6.10 because two conducting sidewalls have been placed at X = a in order to simplify the analysis (X=0 at the center of the microstrip). By setting a >> H, the side walls should not affect the field lines around the conductor, however, the choice of a value for a can have serious effects upon the equation results. In [BAKAG90], a simpler equation for microstrip capacitance is presented which does not require the use of side walls but restricts the width to be less than the height (W < H):

Eq. 15

Both the microstrip and parallel plate capacitance values were calculated using their respective equations and plotted in Figure 6.11, Figure 6.12, and Figure 6.13.

Figure 6.11 - Analytical microstrip capacitance for various dimensions (length = 5 mm)

 

Figure 6.12 - Analytical parallel plate capacitance for a microstrip transmission line structure (length = 5 mm)

Although the parallel plate equation does not accurately model the capacitance in many instances, it does still represent a component of the total capacitance. By subtracting the parallel plate capacitance from the more complete microstrip solutions, the total fringe capacitance may be roughly estimated (Figure 6.13). From the plot it can be seen that fringing is most prevalent when the microstrip is narrow and the separation from the ground plane is relatively small. As the separation increases, the fringing component becomes more stable.

At smaller height values, the fringe field component apparently begins to oscillate as the width increases. This oscillation is due to the sin(np W/2a) component in the analytical expression for the total capacitance (note the minima at W=10 mm due to the a= 500 mm value). As the height increases, the effect of the sin term diminishes due to the sinh and cosh terms in the equation. The oscillation is one of the side effects that occur due to the use of sidewalls in the Pozar analytical model.

Figure 6.13 - Estimated fringing capacitance for microstrip transmission line (length = 5 mm)

Since the parallel plate capacitance may be such a large component of the total capacitance, the effects of fringing field lines for a non-planar conductor may be relatively small at larger dimensions. Figure 6.14 below shows the microstrip parallel plate capacitance as a percentage of the total capacitance. As the microstrip width to height ratio increases, the parallel plate percentage rises dramatically and reduces the effect of fringing field lines even further.

Figure 6.14 - Percentage of total capacitance due to parallel plate capacitance

Single-Conductor Modeling

To obtain an understanding of the relationship between the various spacing parameters and the resulting capacitance values, a series of simulations were performed with QuickCap upon the simple single-conductor model and compared to analytical results obtained using the three capacitance equations (Pozar, Bakaglou and parallel-plate). A wide range of parameters were used in order to represent both square parallel plate structures and long, thin microstrip lines.

Parallel Plate Structure

Typically a parallel plate capacitor has the simplest analytical expression but does not include fringing field lines. Consequently, it is restricted to structures in which the horizontal dimensions are "significantly" larger than the vertical separation (say by a factor of 10 or greater). In order to model more complex structures, the parallel plate capacitance was analyzed using Quickcap and the results compared to the simple analytical expression. The parallel plate structure was not a "true" parallel plate model with two equally sized plates, but rather one using a square conductor in conjunction with the ground plane. This structure permitted easier extrapolation to more complex conductor geometries.

The analysis varied the plate edge length and height over a wide range. From the Quickcap results (Figure 6.15(a)), it can be seen that as the separation decreases and/or the edge length increases, the capacitance also rises. The analytical results (Figure 6.15(b)) using the parallel plate equation also have the same general form but do not match the simulation values except at larger width:height ratios. The error in the analytical values (relative to the QuickCap results) is shown in Figure 6.15(c).

(a) Simulated parallel plate capacitance

(b) Analytical parallel plate capacitance

(c) Error in analytical results

Figure 6.15 - Parallel plate capacitance simulation and analytical results (length = 5 mm)

The discrepancy between the analytical and simulation results is due to fringing at the edges of the conductor. As the edge length is reduced, the proportion of edge length to total plate area increases and thus fringing becomes a larger part of the total capacitance. More important is the relationship between the edge length:height ratio and fringing. As the edge length decreases for a fixed separation, the parallel plate contribution to the capacitance also decreases. However, the total capacitance does not decrease at the same rate and fringing becomes a major contributor to the overall capacitance. Figure 6.16 below shows the relationship between the edge length:separation ratio and the error of the analytical parallel plate capacitance equation.

Figure 6.16 - Error of analytical parallel plate capacitance equation

Microstrip Structure

The microstrip presents a more complex analytical problem due to the inclusion of fringing fields. Two equations for microstrip capacitance (presented earlier) were used for comparison with simulation results. The parallel plate capacitance was also included simply to see how it fared against more detailed equations.

The analysis variables were the microstrip height and width. A dielectric strength e r of 4 was used throughout the analysis to simplify the analytical capacitance calculations, but other values were used occasionally to verify the relative independence of the results. The physical model was the same as for the parallel plate analysis but with different height, width and length parameters.

A microstrip length of 5 mm was used throughout but occasionally replaced by 10 mm in order to ensure that the capacitance per unit length (pF/mm) was constant. Because the microstrip equations were developed for two-dimensional models, they do not account for fringing at the ends of the microstrip and assume that it is "infinitely" long with respect to the width. Under this assumption, the fringing at the ends becomes negligible in comparison to the total capacitance. In order to correlate the two-dimensional equations with results from a three-dimensional simulation tool, the length of the microstrip model was made much larger than the width (5 mm vs. 10 mm, a factor of 500). This reduced the contribution of fringing fields from the line ends to the total capacitance and consequently the model became a quasi-2D structure. The quasi-2D condition was verified by changing the conductor length and comparing the capacitance per unit length values. The analysis results are shown below in Figure 6.17 for the Pozar and Bakaglou microstrip capacitance equations. Although the plot scale factors may be different, the H > W restriction of the Bakaglou equation is clearly evident when compared to the Pozar and simulation results.

(a) Microstrip capacitance (from simulation)

(b) Analytical microstrip capacitance (Pozar equation)

(c) Analytical microstrip capacitance (Bakaglou equation)

Figure 6.17 - Microstrip capacitance simulation and analytical results (length = 5 mm)

The relative errors for both equations and the parallel plate equation are plotted against the width:height ratio in Figure 6.18. The Pozar equations seem to be rather accurate over the entire range although they do have some volatility as the width increases due to the side wall simplification. The Bakaglou model is very accurate up to and even beyond W=H, but quickly falls off. The parallel plate model is quite the opposite, becoming more accurate as the width becomes significantly larger than the vertical separation.

Figure 6.18 - Relative error of analytical microstrip and parallel plate models

Two Dimensional Crossover Modeling and Analysis

Based upon the analysis of capacitance for a single conductor, the next step is to apply the results to more complex structures, namely a simple two-wire crossover. This analysis will identify the impact of the structure parameters upon the overall capacitance values and verify trends based upon empirical knowledge.

Figure 6.19 -Simple quasi-2D crossover model

As with the simple single-conductor structures, the crossover structure (Figure 6.19) is intended to be quasi-2D with the length much greater than the width of any particular segment. The analysis varied the width of the upper conductor, the separation between the conductors and the distance to the groundplane below (for both the entire structure and only the regions outside of the crossover).

The model in Figure 6.20 was developed for use with analytical equations and breaks the crossover into three segments, namely the area immediately around the crossover (C1) and the segments on either side of the intersection (C2A and C2B). Because the conductor-conductor spacing A is much smaller than the distance to the ground plane B, most of the field lines for the lower conductor will terminate on the upper one. This effectively becomes a microstrip structure but with some small error due to the far groundplane. As for the regions on either side of the crossover, depending upon the total height (H) and the width (WOUTSIDE) the capacitance may be modeled as a parallel plate or microstrip structure. Based upon the single conductor analysis, the microstrip model was used because the width:height ratio for the analysis would not fall within the valid regions for the parallel plate capacitance analytic expression.

Figure 6.20 - Discrete analytical model for 2D crossover

Because the values of C2A and C2B depend upon the width of the outside sections, it is not clear just how the upper plane should be divided into segments. Obviously the C1 capacitance will extend beyond the lower conductor width W and occupy some of the area on either side of the immediate crossover region, but unfortunately the analytic expressions do not lend themselves to easily establishing the radius of some region of influence. Consequently, the effective length of the outside segments used in the analytic expressions must be adjusted to provide a close fit with the Quickcap results. As a result, only the crossover capacitance C1 actually provides a uniform measure of the analytic equation accuracy. Due to the use of a random walk algorithm, the Quickcap capacitance extractor cannot provide field lines. It does, however, provide the capacitance between any two conductors (including the ground plane). Using this information, the discrete model capacitance values C1, C2A, and C2B may be easily identified.

Simulation Results

The conductor capacitance values for the simple quasi-2D structure were extracted with Quickcap over a wide range of parameter values in order to determine the effect upon capacitance. The variables in the analysis were the segment widths outside of the crossover region (WCROSS), the height of the external segments above the groundplane (H) and the height of the lower conductor (B). For simplicity, the external segments were given the same length. The lower conductor width was set at 10 mm while the horizontal separation (S) was maintained at 100 mm in order to simplify the analytical equation solutions. The height of the upper conductor in the crossover region (A+B) also remained constant at 500 mm. The length of both conductors was 5 mm in order to reduce the effect of fringing at the ends, thereby emulating a two dimensional structure.

There were two distinct capacitance values obtained from the analysis, specifically the conductor-conductor capacitance (C1) and the capacitance of the segments outside of the crossover region (C2A + C2B). The total capacitance of the upper conductor is the sum of all three components while the lower conductor capacitance is simply C1 plus a small amount of coupling to the ground plane. Figure 6.21 below shows the conductor-conductor coupling C1 while Figure 6.22 contains the capacitance of the upper conductor to ground. The figures contain three plots, each of which correspond to different conductor-conductor offsets. The data in each plot represents the capacitance between the two conductors as the external segment height changes. The four sets of data in each plot correspond to different external segment widths.

(a) Conductor offset = 25 mm

(b) Conductor offset = 50 mm

(c) Conductor offset = 75 mm

Figure 6.21 - Extracted conductor-conductor capacitance for simple non-planar crossover structure

From the plots, it can be seen that the capacitance increases universally as the planarity is decreased. The overall increase is dependent upon the position of the lower conductor and is greatest for the furthest conductor. This is easily explained because the larger offset initially results in lower coupling relative to the other offsets. As the planarity decreases, the capacitance rises to approximately the same level as for the other offsets, but is more dramatic due to the lower initial value. The majority of the increase in capacitance seems to occur up to the point at which the external segment height is equal to the lower conductor height. The capacitance continues to increase as the external segment moves further downward, but this trend appears to stop after the segment is 25 mm below the lower conductor.

(a) Conductor offset = 25 mm

(b) Conductor offset = 50 mm

(c) Conductor offset = 75 mm

Figure 6.22 - Extracted capacitance of segments outside crossover region for simple non-planar crossover structure

Figure 6.22 above shows the coupling of the upper conductor to the ground plane due to the segments outside of the crossover region. Predictably, the position of the lower conductor does not have much of an impact upon the capacitance of the external segments simply because the majority of the conductor-conductor coupling occurs in the immediate region around the crossover. Consequently, the coupling to the ground plane is not affected greatly and the capacitance increases continuously as the height is reduced.

Modeling of External-region Capacitance

Using the Quickcap capacitance results as a goal, the coupling of the upper conductor to the ground plane was modeled using the Pozar and Bakaglou microstrip capacitance equations. Because it was not clear just how far the coupling to the other conductor extended along the upper wire, the length values used in the analytical equations were adjusted to generate results that closely matched the QuickCap results. The fitting to simulation data was coarsely grained, intended only to provide information regarding trends.

The analysis varied the separation between the conductors and the ground plane but maintained a conductor-conductor vertical spacing of 10 mm and a horizontal spacing of 45 mm. The upper conductor width ranged from 400 mm to 1300 mm while the lower conductor was fixed at 10 mm. Figure 6.23 below shows the percent error between the Quickcap simulation results and the Pozar analytical equation while Figure 6.24 shows the same for the Bakaglou estimate. Each plot represents a different conductor-conductor offset and contains data for several (actual) external segment widths. The effective lengths values used are described later in this document.

(a) Conductor-conductor offset = 25 mm

(b) Conductor-conductor offset = 50 mm

(c) Conductor-conductor offset = 75 mm

Figure 6.23 - Error in Pozar analytical estimate of capacitance outside crossover region

The Pozar equation seems to do a fairly good job of estimating the capacitance to ground although much of the accuracy may be attributed to fitting the effective length value to the simulation results. The accuracy increases as the upper conductor width becomes larger, indicating that the crossover region claims a fixed amount of the area outside the actual crossover which becomes a smaller percentage of the total as the width increases. The accuracy with increased width is also greater at lower separations, following the trend depicted previously in Figure 6.18. Although it is not shown, the accuracy of the parallel plate capacitance equation also improves as the height is reduced (from about 60% error down to around 20%).

 

(a) Conductor-conductor offset = 25 mm

(b) Conductor-conductor offset = 50 mm

(c) Conductor-conductor offset = 75 mm

Figure 6.24 - Error in Bakaglou analytical capacitance estimate of area outside crossover region

The Bakaglou equation does not fare quite as well, with significantly increased relative error at lower height values (see Figure 6.24 above). This also agrees with the trend shown in Figure 6.18 in which the error begins to increase greatly as the width:height ratio becomes greater than 1. For small ratios, the error is typically below 10% but is still greater than for the Pozar equation. This is due to the fitting of the data using the Pozar equation rather than Bakaglou, further illustrating the difference between the two expressions.

Effective Length of External Segment

In order to match the extracted results for the capacitance to ground of the upper conductor, the value for the length of the segments outside of the crossover region had to be adjusted. This adjustment is necessary because at low offset values the field lines between the two conductors extend further in the horizontal direction along the upper conductor. As the offset increases, the upper conductor begins to enclose the lower one and consequently shields the external segments from the lower conductor. The effective length values used in the external-segment analysis are shown below in Figure 6.25 for each (original) conductor height. At lower heights, the effective lengths are about the same as the actual external segment lengths mainly because the segment is shielded from the lower conductor. As the height increases, the effective length decreases, reflecting the influence of the lower conductor as the shielding diminishes. When the upper conductor is planar, the effective length is approximately 250 mm less than the actual distance from the lower conductor to the end of the upper one.

Figure 6.25 - Effective length values used in the external segment analysis

Crossover-region Capacitance Analysis

As with the modeling of the external-region, the coupling between the upper and lower conductors was extracted using Quickcap and then compared with the analytical estimates. The Pozar and Bakaglou microstrip equations were applied directly even though the upper conductor was not planar within the crossover region, hence there will be some degree of error in the results. Because the microstrip structure for the crossover depends only upon the length of the lower conductor, there is no effective length parameter that must be determined based upon the numerical capacitance extraction. Consequently, the extracted and analytical capacitance values should be roughly the same.

The lower conductor width was maintained at 10 mm while the upper conductor ranged from 400 mm to 1300 mm on both sides of the crossover. The vertical conductor separation was 10 mm while the horizontal separation between the non-planar segment and the lower conductor was 45 mm on both sides. The length of both conductors was set to 5 mm in order to reduce the effects of fringing from the conductor ends. Unlike the analysis of the upper conductor capacitance to ground, there was no fitting of analytical results to experimental data. Figure 6.26 below shows the percent error between the Quickcap simulation results and the Pozar analytical equation while Figure 6.27 shows the same for the Bakaglou estimate. As with the external region analysis, the three plots represent different conductor-conductor offsets. Although they should have little effect upon the crossover capacitance, the results are also broken down by external-segment width.

(a) Conductor offset = 25 mm

(b) Conductor offset = 50 mm

(c) Conductor offset = 75 mm

Figure 6.26 - Error in conductor-conductor capacitance estimate (Pozar equation)

From the plots, the differences in the conductor separation can be seen by comparing the point where the error begins to decrease (i.e. the "knee" of the curve). The knee represents the point at which the external segments of the upper conductor approach the level of the lower conductor. As the external segments first begin to move downward, they are initially moving closer to the lower conductor and consequently the relative error of the (planar) estimate increases. As the segments move beyond the lower conductor, the error continues to increase up to a point, after which it becomes fairly constant. From the plotted data, it appears that the point at which the error flattens out is approximately 25 mm below the height of the lower conductor.

(a) Conductor offset = 25 mm

(b) Conductor offset = 50 mm

(c) Conductor offset = 75 mm

Figure 6.27 - Error in conductor-conductor capacitance estimate (Bakaglou equation)

The Bakaglou capacitance expression also has the same form as the Pozar equation and approximately the same capacitance. This isn’t particularly surprising because the width:height ratio limitation of the Bakaglou equation isn’t affected as the external segments move closer to the ground plane. The particular choices for conductor width and vertical separation have resulted in a width:height ratio of less than 1, hence the Bakaglou equation is valid. Other choices for the width and separation parameters might not meet the Bakaglou width:height requirement and consequently produce significantly greater error.

Three Dimensional Crossover Analysis

From the previous analysis, it may appear that the development of the quasi-2D model is relatively straightforward and simple but many simulations were required to fine-tune the model and correlate the extracted results with the analytical values. The most significant hindrance to the model development process is the presence of fringing field lines. Because these fields are dependent upon the charge distribution on the conductors, there is no easy way to estimate the results. The solution of Laplace’s equations can provide the exact value for the capacitance but this approach quickly becomes unwieldy and often impossible for all but the simplest structures. Conformal mapping is often employed to translate more complex geometries into simpler ones which lend themselves to relatively easy analytic solutions but this technique also becomes extremely difficult as the level of complexity rises. When the problem is extended from two dimensions into three, the complexity of analytical solutions can become overwhelming. For this reason, the scientific and engineering community has relied upon numerical techniques. Based upon these formidable barriers, the analysis of non-planar crossover structures in three dimensions was undertaken using only numerical analysis tools.

Model Development

Numerous simulations with QuickCap have been performed for various models. The basic form of the structure is a simple rectilinear crossover of first and second level metal as shown in Figure 6.28. Within the model the horizontal separation between the vertical segments of the upper conductor and the lower conductor was varied as well as the height offset values (e.g. the amount of non-planarity).

Figure 6.28 - Three-dimensional view of rectilinear non-planar crossover test structure (not to scale)

While the rectilinear structure is the simplest to implement using the basic QuickCap physical model descriptors, it may produce misleading results due to the unrealistic perfect 90 bends in the upper conductor. Because fringing fields are concentrated at bends and especially corner nodes (primarily due to the resulting charge distribution within the conductor), the lower corners of the upper conductor may generate an excess amount of fringing which could affect the simulation results. Consequently, a different model (Figure 6.29) was developed which replaced the 90 bends with 45 and could provide contrasting data for the rectilinear model.

Figure 6.29 - Three-dimensional view of angled non-planar crossover test structure (not to scale)

Model 1: Rectilinear Structure

The planarity height B and horizontal separation S (Figure 6.30) were varied between the different structures to determine the individual effects. The original planar structure was generated using the reduced interlevel dielectric technology file developed for the Rockwell process. The planarity and separation values are not based upon experimental data and are intended to provide information regarding the general trends of the conductors rather than realistic parasitic capacitances. The metallization heights A and T are based upon the Rockwell specifications while the dielectric thickness H is based upon experimental data. Both conductors were extended horizontally well beyond the crossover region (L for metal-2, metal-1 not shown) in order to provide a more realistic structure and reduce any capacitance due to fringing from the ends of the wires. Because the capacitance is dependent upon the extension of the conductors beyond the crossover region, the increase due to non-planar geometry can only be measured in absolute terms per crossover rather than as a relative percentage.

Figure 6.30 - Two-dimensional cross-section of rectilinear non-planar crossover

For the analysis, the horizontal separation (S) was varied from 0.5 mm to 3.0 mm while the vertical offset (B) ranged from 0.0 mm (e.g. perfectly planar) to 2.0 mm. Based upon the extracted interconnection model for the Rockwell process, the vertical spacing (C) between metal-1 and metal-2 was set to 1.1 mm, the thickness of the lower conductor (A) was 0.65 mm and the upper conductor thickness (T) was 1.4 mm. The conductor extension (L) beyond the crossover region was 30 mm in order to reduce fringing from the ends (the lower conductor has the same length although it is not shown in the figure above). The results from QuickCap are shown below in Figure 6.31 and Table 6.2 and are summarized in Table 6.1. Up to a vertical offset of about 1.0 mm, the increases in capacitance are not especially severe but rise dramatically as the offset continues to grow.

 

Maximum Increase
(0.5
mm horizontal separation)

Maximum Increase
(2.0
mm vertical offset)

Lower Conductor

0.688 fF

0.460 fF

Upper Conductor

3.123 fF

0.605 fF

Miller

1.265 fF

0.533 fF

Table 6.1 - Summary of maximum increase in rectilinear model capacitance

 

Figure 6.31 - Plot of capacitance values for the rectilinear crossover model

 

Horizontal Separation (mm)

Vertical Offset (mm)

Lower Conductor Cap. (fF)

Upper Conductor Cap. (fF)

Miller Capacitance (fF)

0.5

0.0

5.9907

4.9268

1.8319

0.5

0.5

6.0951

5.2328

1.9577

0.5

1.0

6.1769

5.8069

2.2010

0.5

1.5

6.4604

6.8202

2.6003

0.5

2.0

6.6787

8.0502

3.0972

1.0

0.0

6.0044

4.9366

1.8306

1.0

0.5

6.0151

5.1941

1.9436

1.0

1.0

6.1479

5.7994

2.1527

1.0

1.5

6.3188

6.5705

2.4180

1.0

2.0

6.4753

7.8084

2.8176

1.5

0.0

6.0024

4.8948

1.8009

1.5

0.5

6.0563

5.1800

1.9264

1.5

1.0

6.1252

5.7110

2.0800

1.5

1.5

6.2474

6.4600

2.3384

1.5

2.0

6.3031

7.7738

2.7233

2.0

0.0

5.9959

4.9093

1.8192

2.0

0.5

6.0314

5.1580

1.9000

2.0

1.0

6.0780

5.6654

2.0759

2.0

1.5

6.1627

6.3557

2.2869

2.0

2.0

6.2188

7.5226

2.6343

3.0

0.0

5.9729

4.8436

1.8194

3.0

0.5

6.0229

5.1262

1.8831

3.0

1.0

6.0483

5.6859

2.0283

3.0

1.5

6.1597

6.3308

2.2110

3.0

2.0

6.2951

7.4454

2.5643

Table 6.2 - Upper conductor, lower conductor, and Miller capacitances for the rectilinear model

While the capacitance between the conductors (e.g. the Miller capacitance) increases significantly, the lower conductor capacitance grows much more slowly. As shown in Figure 6.32 below, the ratio of Miller capacitance to the total capacitance for the lower conductor increases as the vertical offset increases, indicating that the capacitance to ground is decreasing at a slightly lower rate than the Miller capacitance rate of increase. For the upper conductor, the Miller capacitance is a relatively constant percentage of the total capacitance (about 36%) while it becomes an increasingly larger part of the lower conductor capacitance (rising from about 30% to 40-45%). The relationships hold for all horizontal separations but decrease slightly as the horizontal separation increases (as evidenced by the growing separation in the individual lines towards the right side of the plot).

Figure 6.32 - Percentage of Miller capacitance to total (rectilinear model)

The explanation for the increase in the Miller capacitance is simple: as the upper conductor becomes increasingly non-planar, the distance between the two conductors is reduced and consequently the coupling between the two nodes increases. Figure 6.33 below shows the differential change in Miller capacitance for each height offset value as the horizontal separation is increased. Not surprisingly, the maximum differential change in the Miller capacitance occurred when the horizontal separation was small and the offset height was large. As either the horizontal separation increases or the vertical offset decreases, the sensitivity of the Miller capacitance is also reduced.

Figure 6.33 - Differential changes in Miller capacitance between successive horizontal separations for different height offsets (rectilinear model)

Model 2: 45 Angled Structure

In order to determine if fringing due to the sharp 90 bends in the rectilinear model were skewing the simulation results, a model with only 45 angles was developed. As shown in Figure 6.34 below, the angled structure was derived from the rectilinear model by simply rotating the vertical segment 45 about its center. This effectively increased the horizontal separation for the lower part of the upper conductor by B*cos45 while decreasing the horizontal separation at the top by the same amount. Later analyses were performed which moved the angled structure away from the center by B*cos45 in order to obtain the same minimum horizontal separation for the topmost segment of the upper conductor used in the rectilinear model.

Figure 6.34 - Dimensions for angled non-planar 2-D crossover model

The sensitivity of the new model is shown below in Figure 6.35. By inspection, the differential Miller capacitance trends established by the rectilinear model (Figure 6.33) are obviously not the same as for the angled model at small horizontal separations and large vertical offsets. This is most evident by the difference (between vertical offsets of 0.5 mm and 1.0 mm) in Miller capacitance for a horizontal separation of 2.0 mm.

Figure 6.35 - Differential changes in Miller capacitance for different height offsets and horizontal separations (angled model)

For the rectilinear model, the Miller capacitance moving from a horizontal separation of 0.5 mm to 1.0 mm dropped by 50% while the angled model had a drop of less than 30%. The diminished sensitivity of the angled model suggests that the rectilinear structure is overly sensitive when the conductors are close together but settles down when the separation increases (and vice versa for the vertical offset). The actual data for the upper conductor, lower conductor and Miller capacitances is shown in Figure 6.34 and Table 6.4. The maximum increases in capacitance are summarized below in Table 6.3.

Capacitance

Max. Increase
(0.5
mm horizontal separation)

Max. Increase
(2.0
mm vertical offset)

Lower Conductor

0.324 fF

0.190 fF

Upper Conductor

2.870 fF

0.318 fF

Miller

0.920 fF

0.226 fF

Table 6.3 - Summary of maxiumum increase in capacitance for the angled model

Figure 6.36 - Plot of capacitance values for angled crossover model

 

Horizontal Separation (mm)

Vertical Offset (mm)

Lower Conductor Cap. (fF)

Upper Conductor Cap. (fF)

Miller Cap. (fF)

0.5

0.0

5.9573

4.9231

1.7958

0.5

0.5

6.0902

5.3111

1.9964

0.5

1.0

6.0475

5.7029

2.0813

0.5

1.5

6.1165

6.4585

2.3046

0.5

2.0

6.2814

7.7924

2.7375

1.0

0.0

5.961

4.8759

1.8238

1.0

0.5

6.0431

5.2578

1.9784

1.0

1.0

6.0904

5.7664

2.1095

1.0

1.5

6.164

6.6139

2.3486

1.0

2.0

6.471

7.8303

2.8254

1.5

0.0

5.9737

4.9829

1.8195

1.5

0.5

6.1478

5.2197

1.9572

1.5

1.0

6.1363

5.7468

2.1167

1.5

1.5

6.1767

6.529

2.3637

1.5

2.0

6.3939

7.7052

2.7799

2.0

0.0

6.0071

4.9263

1.8092

2.0

0.5

6.0749

5.207

1.926

2.0

1.0

6.0801

5.7283

2.0936

2.0

1.5

6.114

6.4331

2.3095

2.0

2.0

6.3061

7.6168

2.7114

3.0

0.0

5.9834

4.9316

1.8185

3.0

0.5

6.0147

5.1996

1.9103

3.0

1.0

6.0753

5.6408

2.0267

3.0

1.5

6.1009

6.389

2.2418

3.0

2.0

6.2935

7.5119

2.5993

Table 6.4 - Upper conductor, lower conductor, and Miller capacitances values for angled model

Although the differential changes in the Miller capacitance varied between the two models, the general relationship between the Miller capacitance and the total node capacitance (Figure 6.37) below has remained relatively the same as for the rectilinear model.

Figure 6.37 - Percentage of Miller capacitance to total (angled model)

Despite the differences between the two models, the important question is what effect will the choice of models have upon the total capacitance estimate. In Figure 6.38, the difference between the two estimates is plotted as a percentage of the total capacitance of the rectilinear model . At narrow horizontal separations and larger vertical offsets, the difference in capacitance can reach almost 15% of the node total, but it quickly levels off to a much lower value of typically 2% or less. In general, the choice of models is not exceptionally unimportant.

 

Figure 6.38 - Effect of model choice upon total net capacitance (relative to capacitance for rectilinear model)

Effect of Non-Planarity upon Differential Wires

The previous analyses have examined the "draping" effect of non-planar interconnections upon single-conductor crossover structures. This investigation is not complete, however, without some mention of the impact of non-planar interconnections upon differential wiring. This subsection describes the behavior of differential signals and discusses the impact of non-planar interconnect upon parasitic capacitance.

Differential Signal Mutual Capacitance

Mutual coupling between the two components of a differential signal adds another level of complexity to parasitic capacitance analysis. When the logical state of a differential signal changes, the potential of both components must switch to the opposite value, effectively doubling the voltage swing. Single-ended signals may also encounter the same situation when an adjacent signal switches simultaneously in the opposite direction, but the total length of all adjacent wires is typically less than for a differential signal routed in adjacent tracks. Furthermore, the probability that a digital signal switches to either logical state is 50%, hence half of the nodes that are adjacent to the single-ended signal will move in the same direction as the signal itself and contribute nothing to the delay. The mutual capacitance to non-switching signals will remain the same while signals switching in the opposite direction will effectively double the mutual capacitance.

Effect of Differential Signal Switching

The essential characteristic of differential signals are two potentials that establish the value of a signal without using an external reference potential. Because both components of a differential signal switch simultaneously and in opposite directions, the coupling between two differential signals is more complex than for single-ended signals. The coupling due to switching events may be classified by the number of simultaneous events, e.g. separate or simultaneous signal switching events.

When only one differential signal is switching, the coupling between the upper and lower signals remains the same as the static capacitance. When both signals switch simultaneously, the intersignal capacitance between all four components changes but the overall coupling remains roughly the same. For example, consider one half of a differential signal in the crossover structure. When the signal switches, the two components of the lower signal also switch at the same time. Consequently, the coupling to one of the lower signals is doubled (due to the voltage swing in the opposite direction) but the coupling to the other is negated (due to the voltage swing in the same direction). For differential signals, the overall parasitic capacitance remains roughly the same regardless of the signal transients.

One situation of particular importance occurs when a single-ended signal crosses a differential signal. If a transition occurs on both signals simultaneously, the coupling between each half of the differential pair will be different and result in doubled capacitance for one node and no capacitance for the other. The imbalanced capacitance could then lead to intrasignal skew and add differential-mode noise to the signal.

Differential Pair "Screening" and the "Draping Effect"

Another consequence of differential signal crossovers is the reduction of the intrasignal coupling (e.g. the mutual capacitance between the differential signal pair). The other signal trace (not necessarily differential) in the crossover couples with the differential signal components and effectively reduces or "screens" the mutual capacitance of the differential pair. When two differential signals form a crossover, the screening occurs for both signals.

The screening effect can be beneficial and reduce the effective capacitance of differential signals. The mutual capacitance between the components of a differential signal are effectively doubled when the signal changes state. In contrast, the coupling between two differential signals is not dependent upon the signal transitions. Consequently, by replacing the mutual capacitance (between components of a differential pair) with crossover capacitance (from another differential signal), the effective coupling during switching is reduced. Furthermore, the increase in coupling due to the "draping effect" will further reduce the mutual capacitance of the differential pairs and improve the switching performance.

Effect of Non-Planarity upon Realistic Interconnect

Although an estimate of the increase in crossover capacitance was established in the previous section, the impact of the results cannot be determined without examining actual fabricated interconnections within a design. To conclude the discussion of capacitance modeling for non-planar interconnection processes, we’ll examine actual wiring statistics taken from the F-RISC/G chip set and determine the increase in capacitance due to the use of planar models to represent a non-planar process.

F-RISC/G Interconnection Statistics

Due to the high congestion within the standard cell areas, the interconnection statistics for F-RISC/G were taken using the channel wiring tracks within a standard cell area. Typically the wires in these areas range from very short to very long and should provide a wide range of the crossovers-per-unit-length and crossovers-per-net metrics. A special CAD tool was developed, called CHANNEL_INFO, which examined the interconnection and recorded the total wire length as well as the total number of crossovers. The detailed information was then fed into a spreadsheet and analyzed.

For the analysis, the two largest standard cell areas were selected and were examined by CHANNEL_INFO. Due to the data structure employed by the Compass CAD tool suite, only the interconnection within the standard cell area was analyzed. External segments were ignored due to the difficulty in flattening the wire structure. The analysis of each area took several hours due to the sheer size of the file and the iterative procedure used to check for crossovers.

(a) Instruction decoder standard cell area

(b) Datapath standard cell area

Figure 6.39 - Number of crossovers per wire for the two largest F-RISC/G standard cell areas (internal nets only)

The distribution of crossovers per net for each area is shown in Figure 6.39. The majority of nets have relatively few crossovers and consequently will most likely not be affected by the small increase in capacitance per crossover. As the crossover count increases, though, the additional loading per crossover may become significant. Based upon the wiring statistics in Table 6.5 below and the maximum capacitance increase per crossover from the previous section, estimates may be made regarding the total capacitance increase per net. These estimates are shown in Table 6.6.

Area

Average # of crossovers per wire

Median # of crossovers per wire

Maximum # of crossovers per wire

Datapath

104.5

8.08

800

Instruction Dec.

85.9

6.95

728

Area Average # of segments per wire Average wire length Average # of crossovers per unit length
Datapath 8.08 2020.3 0.052
Instruction Dec. 6.95 1776.7 0.052

 

Inst. Decoder 0.5 mm Crossover Horizontal Sep. 2.0 mm Crossover Vertical Offset
  Avg. Increase Max. Increase Avg. Increase Max. Increase
Lower Cond. 27.6 fF 235.9 fF 16.2 fF 138.3 fF
Upper Cond. 244.2 fF 2.089 pF 27.1 fF 231.5 fF
Miller cap. 78.3 fF 669.8 fF 19.2 fF 164.5 fF
         
Datapath 0.5 mm Crossover Horizontal Sep. 2.0 mm Crossover Vertical Offset
  Avg. Increase Max. Increase Avg. Increase Max. Increase
Lower Cond. 33.9 fF 259.2 fF 19.9 fF 152.0 fF
Upper Cond. 299.9 fF 2.30 pF 23.6 fF 180.8 fF
Miller cap. 96.1 fF 736.0 fF 23.6 fF 180.8 fF

Table 6.6 - F-RISC/G projected average and maximum wire capacitance increases due to non-planar interconnect

Although the maximum capacitance increase per net may seem rather large and ominous in terms of the F-RISC/G project, it should be noted that this number is simply a projected value based upon certain assumptions regarding the interconnection process, specifically the actual values for the vertical offset and horizontal separation. While most of the values used in the interconnection analysis are based upon the Rockwell process, the specific dimensions regarding the non-planar crossover structure are entirely hypothetical. In this light, this work stands as a hypothetical investigation and does not reflect directly upon the Rockwell process.

Summary

Capacitance estimation is a vital part of modern designs due to the high circuit speeds and small integrated circuit dimensions. This problem is worse for semi-insulating substrates since most of the coupling occurs between wires rather than to the distant ground plane. Analytical models for simple structures have been around for quite some time but they tend to often be limited in their accuracy due to fringing effects. The parallel plate equation and two microstrip equations were evaluated in terms of accuracy relative to extracted results from a three-dimensional capacitance simulator. These equations were then used to create a simple model of a quasi-two-dimensional non-planar crossover that treated both the crossover region and the external regions as microstrip transmission lines. The accuracy of the model was within 15% to 30% depending upon the microstrip equation used.

A three-dimensional non-planar crossover was characterized in terms of horizontal separation and vertical offset using the QuickCap capacitance extraction tool. Two models were developed which used different structures for the upper conductor in order to examine if the model structure was skewing the results due to excess fringing. The models were found to be roughly equivalent as the horizontal and vertical spacing increased while the rectilinear model had somewhat greater coupling at smaller separations.

For the non-planar 3-D structure, the maximum increase in crossover capacitance was found to be 2.87 fF at minimal offsets of 0.5 mm, but it dropped quickly to 0.318 fF as the separations increased to 2.0 mm. These values were then applied to actual F-RISC/G standard cell wiring statistics to generate estimates for the average and maximum capacitance increase per net under different circumstances. On average, for a 2.0 mm horizontal separation and a vertical (non-planarity) offset of 2.0 mm, the capacitance increase was around 20 fF per net. It should be noted that these estimates are based upon hypothetical values of horizontal separation and vertical offset. No direct (e.g. visual) data is available regarding the physical crossover characteristics of actual fabricated structures. Actual capacitance measurements have been made but cannot be used to extrapolate crossover parameters because very few of the structure parameters are known or easily determined (e.g. the conductor widths and lengths).