- Adar, A. and R. Ramachandran, "An HBT
Wideband VCO," IEEE MTT-S Digest, pp.
- Asbeck, P.M. et al., "Application of
Heterojunction Bipolar Transistors to High Speed,
Small-Scale Digital Integrated Circuits," GaAs IC
Symposium, pp. 133-136, 1984.
- Bakaglou, H.B., Circuits,
Interconnections and Packaging for VLSI, pp. 277-278,
Reading, Massachusetts: Addison-Wesley, 1990.
- Bohr, Mark, Interconnect Scaling and
the Challenges of Copper, Intel Corporation,
presentation at Rensselaer Polytechnic Institute, July
- Buchwald, Aaron W. et al., "A
6-GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs
Heterojunction Bipolar Transistors," IEEE Journal
of Solid-State Circuits, pp. 1752-1761, vol. 27, no.
12, December 1992.
- Campbell, Peter M. et al., "A
High-Bandwidth Voltage Controlled Oscillator (VCO) with a
Frequency-Multiplied/Divided Range of 0.25-20 GHz
Implemented in a GaAs HBT Process," Proceedings
of the Eighth Annual IEEE International ASIC Conference,
pp. 49-52, September 1995.
- Campbell, Peter M. et al., "A
Very-Wide Bandwidth Digital VCO Implemented in GaAs HBTs
Using Frequency Multiplication and Division," 17th
Annual GaAs IC Symposium Technical Digest, pp.
311-314, October 1995.
- Campbell, Stephen A., The Science and
Engineering of Microelectronic Fabrication, pp.
415-417, New York: Oxford University Press, 1996.
- Chang, D. and R. Hook, "A Sub-Five
Nanosecond ECL 128x18 Three Port Register File," Bipolar
Circuits and Technology Meeting, pp. 98-100, 1987.
- Chao, C.-C. and B.A. Wooley, "A 1.3ns
32-Word x 32-Bit Three-Port BiCMOS Register File," IEEE
Journal of Solid-State Circuits, pp. 758-766, vol.
31, no. 6, June 1996.
- Chuang, C.T. et al., "A Subnanosecond
5-kbit Bipolar ECL RAM," IEEE Journal of
Solid-State Circuits, pp. 1265-1267, vol. 23, no. 5,
- Cooperman, Michael, "High Speed
Current Mode Logic for LSI," IEEE Journal of
Solid State Circuits, vol. CAS-27, no. 7, pp.
626-635, July 1980.
- Degerstrom, Mike, Mayo Institute, e-mail
communication to John F. McDonald, August 5, 1996.
- Dehhimy, Ira, "Gallium Arsenide Joins
the Giants," IEEE Spectrum, vol. 32, no. 2,
pp. 33-40, February 1995.
- Dillinger, Thomas E., VLSI Engineering,
pp. 56-90, Englewood Cliffs, New Jersey: Prentice-Hall.
- Edelstein, D.C., G.A. Sai-Halasz and Y.-J.
Mii, "VLSI on-chip interconnection performance
simulations and measurements," IBM Journal of
Research and Development, vol. 39, no. 4, July 1995.
- Garg, Atul, "GaAs HBT Interconnect
Characterization and Design of a Dense Package for a High
Speed RISC Processor," Doctoral thesis,
Rensselaer Polytechnic Institute, December 1996
- Gilbert, B., "A New High-Performance
Monolithic Multiplier Using Active Feedback," IEEE
Journal of Solid-State Circuits, pp. 364-373, vol.
SC-9, December 1974.
- Grebne, Alan, Bipolar and MOS Analog
Integrated Circuit Design, pp. 451-479, New York:
John Wiley & Sons, 1984.
- Greub, Hans J., Apparatus for Skew
Compensating Signals, patent no.4833695, issued May
- Greub, H.J. et al.,
"High-performance Standard Cell Library and Modeling
Technique for Differential Advanced Bipolar Current Tree
Logic," IEEE Journal of Solid State Circuits,
vol. 26, no. 5, pp. 749-762, May 1991.
- Greub, Hans J., "Switching Device
Models Version 1.0 (4/22/96)," E-mail describing
switching device model derivation and verification,
April 22, 1996.
- Hennessy, J. et al., "Design
of a High Performance VLSI Processor," Proceedings
of the 3rd Caltech Conference on
VLSI, pp. 33-54, Computer Science Press, March 1983.
- Hirose, Toshihiko et al., "A
20ns 4Mb CMOS SRAM with Hierarchical Word Decoding
Architecture," IEEE International Solid-State
Circuits Conference Digest of Technical Papers, pp.
132-133, February 1990.
- Katevenis, Manolis G. H., Reduced
Instruction Set Computer Architectures for VLSI,
Cambridge, Massachusetts: MIT Press, 1984.
- Kkatibzadeh, M.A et al., "High
Power and High Efficiency Monolithic HBT VCO
Circuit," IEEE GaAs IC Symposium, pp. 11-14,
- Kroemer, Herbert, "Heterostructure
Bipolar Transistors and Integrated Circuits," Proceedings
of the IEEE, vol. 70, no. 1, pp.13-25, January 1982.
- Le Coz, Y.L, R.B. Iverson, H.J. Greub,
P.M. Campbell and J.F. McDonald, "Application of a
Floating-Random-Walk Algorithm for Extracting
Capacitances in a Realistic HBT Fast-RISC RAM Cell,"
Proceedings of the Eleventh International VLSI
Multilevel Interconnection Conference (VMIC), pp.
542-544, June 1994.
- Lee, Frank, Rockwell International., e-mail
message to John F. McDonald, May 31, 1995.
- Long, Stephen I. and Steven E. Butner, Gallium
Arsenide Digital Integrated Circuit Design, pp.
69-73, New York: McGraw-Hill, 1990.
- Loy, James R., "Managing Differential
Signal Placement," Ph.D Thesis, Rensselaer
Polytechnic Institute, Troy, NY, August 1993.
- Maier, Cliff, "A Cache Hierarchy for
Yield-Limited Technologies," Doctoral thesis,
Rensselaer Polytechnic Institute, 1996.
- McDonald, John F. et al.,
"F-RISC/G - A 1.0 GigaOPS Fast RISC Processor for
Superworkstation and TeraOPS Parallel Processing
Applications," semi-annual report to DARPA,
October 1992-March 1993.
- OEA International, METAL - Two and
Three Dimensional Interconnect Simulator, 1991.
- Miyanaga, Hiroshi et al., "A
1.5 ns 1K Bipolar RAM Using Novel Circuit Design and
SST-2 Technology," IEEE Journal of Solid-State
Circuits, pp. 291-298, vol. SC-19, no. 3, June 1984.
- Murarka, Shyam, Metallization: Theory
and Practice for VLSI and ULSI, pp. 195-211, Boston:
- Nah, K. et al., "F-RISC/G:
AlGaAs/GaAs HBT Standard Cell Library," Proceedings
of the 1991 IEEE International Conference on Computer
Design, pp. 297-300, October 1991.
- Nah, K.S., "An Adaptive Clock Deskew
Scheme and a 500 ps 32 by 8 Bit Register File for a High
Speed Digital System," Doctoral thesis,
Rensselaer Polytechnic Institute, August 1994.
- Nakase, Yasunobu et al., "A
2-ns 16K Bipolar ECL RAM with Reduced Word-Line Voltage
Swing," IEEE Journal of Solid State Circuits,
pp. 518-524, vol. 26, no. 4, April 1991.
- Nambu, Hiroaki et al., "A
0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM," IEEE
Journal of Solid State Circuits, pp. 491-499, vol.
30, no. 4, April 1995.
- Philhower, Robert, "Spartan RISC
Architecture for Yield-Limited Technology," Doctoral
thesis, Rensselaer Polytechnic Institute, August1993.
- Pozar, David M., Microwave Engineering,
pp. 183-194, Reading Massachusetts: Addison-Wesley, 1990.
- Iverson, R.B. and Y.L. Le Coz, Users'
Guide for QuickCap™ version 1.1, Random Logic
- Rocchi, Mark, High-Speed Digital IC
Technologies, pp. 296-297, New York: Artech House,
- Schmidt, L. et al., "New
High-Speed Bipolar XOR Gate with Absolutely Symmetrical
Circuit Configuration," Electronics Letters,
pp. 430-431, vol. 26, 1990.
- Soyuer, Mehmet and James D. Warnock,
"Multigigahertz Voltage-Controlled Oscillators in
Advanced Silicon Bipolar Technology," IEEE
Journal of Solid-State Circuits, pp. 668-670, vol.
27, no. 4, April 1992.
- Sze, S.M., Physics of Semiconductor
Devices, second edition, pp.182-3, New York: John
Wiley and Sons, 1981.
- Tamba, N. et al., "A 1.5-ns
256-kb BiCMOS SRAM with 60-ps 11-K Logic Gates," IEEE
Journal of Solid-State Circuits, pp. 1344-1352, vol.
29, no. 11, November 1994.
- Wang, Nan-Lei and Wu-Jing Ho, "X-Band
HBT VCO with High-Efficiency CB Buffer Amplifier," IEEE
Journal of Solid-State Circuits, pp. 1439-1443, vol.
27, no. 10, October 1992.
- Weste, Neil H.E. and Kamran Eshraghian, Principles
of CMOS VLSI Design: a Systems Perspective, second
edition, pp. 407-417, Reading, Massachusetts:
- Wong, C.P., Polymers for Electronic and
Photonic Applications, pp. 129-165, Boston: Academic
- Yoshimoto, M. et al., "A
Divided Word-Line Structure in the Static RAM and its
Application to a 64k Full CMOS RAM," IEEE Journal
of Solid-State Circuits, pp. 479-485, vol. SC-18,
- Zhang, Xiaonan, "Coupling Effects on
Wire Delay," IEEE Circuits & Devices, pp.
12-18, November 1996.