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APPENDIX A

Package I/O Map

APPENDIX B

AutoCAD Drawings

Figure B.1: Assembly of the test jig.


Figure B.2: Isometric view of the assembly.

Figure B.3: Picture of the heat sink.

Figure B.4: 3-D view of the heat sink with dimensions.

Figure B.5: Top mounting plate of the heat sink.

Figure B.6: Thermoelectric cooler module.

APPENDIX C

Matlab Program Files for Thermal Simulation

% Filename : hbt7.m


% This file calculates the temperature distribution due to a single emitter


% stripe around its center.

% Functions called - avgtemp

% - tempxy_layers


clear;

N = 100; % Number of grid points

delta = 0.199; % Increment in X and Y directions in microns

He = 25; % Thickness of epoxy in microns

k = 46; % Thermal conductivity in W/m.K

ke = 3.937; % Thermal conductivity of epoxy in W/m.k

L = 1.7; % Emitter stripe length (in microns) along X direction

% with center at (0,0)

W = 1.2; % Emitter stripe width (in microns) along Y direction

% with center at (0,0)

T0 = 277; % Chip backside temperature in K

n = -1.25; % Empirical number for Thermal conductivity variation

z = 1.5; % Empirical number for vertical distance

% Note: L and W are deliberately augmented by .001 micron to

% avoid a singularity in the computation

% Temperature Calculation Based on a Surface Source

% Note: Multiplication of 1E6 ensures the use of all the further

% units in microns.

% Generate X and Y array.

for i=(N/2)+1:N, X(i)=(i-(N/2))*delta; end

for i=1:N/2, X(i)= -1*X(N-i+1); end

for j = 1:N

Y(j) = X(N-j+1);

end

% Case 1: Calculate distribution for H = 75 um, P = 2.8mW

% Calculate TLW (temperature at each X and Y)

x0 = 0;

y0 = 0; % locations of the source = (x0,y0)

L2 = L/2;

W2 = W/2;

Power = [0.5; 1.0; 1.5; 2.3; 2.8; 3.0; 5.0; 10.0; 20.0;]; % in mW

CLW1 = (Power*1E6*1E-03)/(2*pi*k*L*W);

CLW1_layers = (Power*1E6*1E-03)/(2*pi*ke*L*W);

Thickness = [5; 10; 25; 50; 75; 100; 200; 300; 400; 500; 600;];

for l=5:5

for k=5:5

for i=1:N

for j=1:N

TLW(j,i)= tempxy_layers(CLW1(l), CLW1_layers(l), x0, y0, X(i), Y(j), L2, W2, Thickness(k), k,He,ke,T0,n,z);

end

end

Thickness(k)

avg_temp(l,k) = avgtemp (TLW,X,Y,L2+0.5,W2+0.5,N)

peak_temp(l,k) = max (max (TLW))

end

devpower = Power(l)

end

save hbt7_P_28_H_75

surf(X,Y,TLW);

xlabel('X(microns)');

ylabel('Y(microns)');

zlabel('Temperature Rise (deg C)'); pause;

surf(X(26:75),Y(26:75),TLW(26:75,26:75));

xlabel('X(microns)');

ylabel('Y(microns)');

zlabel('Temperature Rise (deg C)'); pause;

plot(X,TLW(:,50),'-w'); hold on;

plot(X,TLW(:,50),'ow');

xlabel('Distance from Source Center(microns)');

ylabel('Temperature Rise (deg C)'); pause;

for l=1:9

for k=1:11

for i=1:N

for j=1:N

TLW(j,i) = tempxy_layers(CLW1(l), CLW1_layers(l), x0, y0, X(i), Y(j), L2, W2, Thickness(k), k, He, ke, T0, n, z);

end

end

Thickness(k)

avg_temp(l,k) = avgtemp(TLW,X,Y,L2+0.5,W2+0.5,N)

peak_temp(l,k) = max(max(TLW))

end

devpower = Power(l)

end

save hbt7_P_all_H_all

% Filename : hbt7_twodevices.m


% This file calculates the temperature distribution due to an adjacent emitter .


% Functions called - avgtemp

% - tempxy_layers


clear; N = 25;

delta = 0.199; % delta is the increment in X and Y in microns

H = 600; % die thickness in microns

He = 50; % epoxy thickness in microns

P = 2.8E-03; % Power in mW

k = 46; % Thermal Conductivity in W/m.K

ke = 3.937; % Thermal conductivity of epoxy in W/m.k

L = 1.7; % Emitter Stripe Length (in microns) along X direction

% with center at (0,0)

W = 1.2; % Emitter Stripe Width (in microns) along Y direction

% with center at (0,0)

T0 = 277; % T0 is the chip backside temperature

n = -1.25; % empirical number

z = 1.5; % empirical number for distance

% Note: L and W are deliberately augmented by .001 micron to

% avoid a singularity in the computation

% Temperature Calculation Based on a Surface Source %%%%%%

% Note: Multiplication of 1E6 ensures the use of all the further units in microns.

for i=(N/2)+1:N, X(i)=(i-(N/2))*delta; end

for i=1:N/2, X(i)= -1*X(N-i+1); end

for j = 1:N, Y(j) = X(N-j+1); end

% Calculate TLW

x0 = 0; y0 = 0; % locations of the source = (x0,y0)

L2 = L/2; W2 = W/2;

Power = [0.5; 1.0; 1.5; 2.0; 2.8; 5.0; 10.0; 20.0;]; % in mW

CLW1 = (Power*1E6*1E-03)/(2*pi*k*L*W);

CLW1_layers = (Power*1E6*1E-03)/(2*pi*ke*L*W);

L2array = [L2; L2; L2; L2; L2+0.5; L2+0.65; L2+0.8; L2+0.9];

W2array = [W2; W2; W2; W2; W2+0.5; W2+0.65; W2+0.8; W2+0.9];

LocationX = [0; 3; 4.5; 6; 7.5; 9; 12; 15; 18;];

LocationY = [0; 3; 4.5; 6; 7.5; 9; 12; 15; 18;];

Thickness = [5; 10; 25; 50; 75; 100; 200; 300; 400; 500; 600;]; %in ums

for u=1:9

for v=1:9

for k=5:5

for l=5:5

for i=1:N

for j=1:N

TLW(j,i) = tempxy_layers(CLW1(k), CLW1_layers(k), x0, y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),LocationX(u),LocationY(v),X(i),Y(j),L2,W2,Thickness(l),k,He,ke,T0,n,z);

end; end

avg_temp(u,v) = avgtemp(TLW,X,Y,L2array(k),W2array(k),N)

avg_temp_increase(u,v)= avg_temp(u,v) - (avg_temp(1,1)/2);

peak_temp(u,v) = max(max(TLW))

peak_temp_increase(u,v)= peak_temp(u,v) - (peak_temp(1,1)/2);

end; end; end; end

save hbt7twodevices_P_28_H_75

avg_temp_increase(1,1) = 0; peak_temp_increase(1,1) = 0;

plot(LocationX(2:9),avg_temp_increase(2:9,1),'-w');

% Filename : hbt7_3x3array.m


% This file calculates the temperature distribution due to a 3x3 array of emitter


% stripes at the center emitter.

% Functions called - avgtemp

% - tempxy_layers


clear;

N = 250;

delta = 0.199; % delta is the increment in X and Y in microns

H = 600; % die thickness in microns

He = 50; % epoxy thickness in microns

P = 2.8E-03; % Power in mW

k = 46; % Thermal Conductivity in W/m.K

ke = 3.937; % Thermal conductivity of epoxy in W/m.k

L = 1.7; % Emitter Stripe Length (in microns) along X direction

% with center at (0,0)

W = 1.2; % Emitter Stripe Width (in microns) along Y direction

% with center at (0,0)

T0 = 277; % T0 is the chip backside temperature

n = -1.25; % empirical number

z = 1.5; % empirical number for distance

%

% Note: L and W are deliberately augmented by .001 micron to

% avoid a singularity in the computation

%

%%%%%%% Temperature Calculation Based on a Surface Source %%%%%%

CLW = (P*1E6)/(2*pi*k*L*W);

CLW_layers = (P*1E6)/(2*pi*ke*L*W);

%

% Note: Multiplication of 1E6 ensures the use of all the further

% units in microns.

%

for i=(N/2)+1:N, X(i)=(i-(N/2))*delta; end

for i=1:N/2, X(i)= -1*X(N-i+1); end

for j = 1:N

Y(j) = X(N-j+1);

end

% Calculate TLW

x0 = 0;

y0 = 0; % locations of the source = (x0,y0)

L2 = L/2;

W2 = W/2;

Power = [0.5; 1.0; 1.5; 2.0; 2.8; 5.0; 10.0; 20.0;]; % in mW

CLW1 = (Power*1E6*1E-03)/(2*pi*k*L*W);

CLW1_layers = (Power*1E6*1E-03)/(2*pi*ke*L*W);

L2array = [L2; L2; L2; L2; L2+0.5; L2+0.65; L2+0.8; L2+0.9];

W2array = [W2; W2; W2; W2; W2+0.5; W2+0.65; W2+0.8; W2+0.9];

%LocationX = [0; 3; 4.5; 6; 7.5; 9; 12; 15; 18;];

%LocationY = [0; 3; 4.5; 6; 7.5; 9; 12; 15; 18;];

Thickness = [5; 10; 25; 50; 75; 100; 200; 300; 400; 500; 600;]; %in ums

for l=5:5

for k=5:5

for i=1:N

for j=1:N

TLW(j,i) = tempxy_layers(CLW1(k), CLW1_layers(k), x0, y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) +

tempxy_layers(CLW1(k),CLW1_layers(k),16,0,X(i),Y(j),L2,W2,Thickness(l),k,He,ke,T0,n,z)+ ...

tempxy_layers(CLW1(k), CLW1_layers(k),-19, 0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) +

tempxy_layers(CLW1(k),CLW1_layers(k),-19, 16, X(i), Y(j), L2, W2, Thickness(l), k, He, ke,T0,n,z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),0,16,X(i),Y(j),L2,W2,Thickness(l),k,He,ke,T0,n,z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),16,16,X(i),Y(j),L2,W2,Thickness(l),k,He,ke,T0,n,z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),-19,-13, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),16,-13, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),0,-13, X(i), Y(j), L2, W2, Thickness(l), k,He,ke,T0,n,z);

end

end

Thickness(l)

avg_temp(l) = avgtemp(TLW,X,Y,L2array(k),W2array(k),N)

peak_temp(l)= max(max(TLW))

end

end

save hbt7_3x3arrayP28H75N250

% Filename : hbt7_bigarray.m


% This file calculates the temperature distribution due to a big array


% (1.6 mm x 1.3 mm) of emitter stripes at the center emitter.

% Functions called -avgtemp

% -tempxy_layers


clear;

N = 25;

array_size = 100;

delta = 0.199; % delta is the increment in X and Y in microns

H = 600; % die thickness in microns

He = 50; % epoxy thickness in microns

P = 2.8E-03; % Power in mW

k = 46; % Thermal Conductivity in W/m.K

ke = 3.937; % Thermal conductivity of epoxy in W/m.k

L = 1.7; % Emitter Stripe Length (in microns) along X direction

% with center at (0,0)

W = 1.2; % Emitter Stripe Width (in microns) along Y direction

% with center at (0,0)

T0 = 277; % T0 is the chip backside temperature

n = -1.25; % empirical number

z = 1.5; % empirical number for distance

% Note: L and W are deliberately augmented by .001 micron to

% avoid a singularity in the computation

%%%%%%% Temperature Calculation Based on a Surface Source %%%%%%

CLW = (P*1E6)/(2*pi*k*L*W);

CLW_layers = (P*1E6)/(2*pi*ke*L*W);

% Note: Multiplication of 1E6 ensures the use of all the further

% units in microns.

for i=(N/2)+1:N, X(i)=(i-(N/2))*delta; end

for i=1:N/2, X(i)= -1*X(N-i+1); end

for j = 1:N, Y(j) = X(N-j+1); end

% Calculate TLW

x0 = 0; y0 = 0; % locations of the source = (x0,y0)

L2 = L/2;

W2 = W/2;

Power = [0.5; 1.0; 1.5; 2.0; 2.8; 5.0; 10.0; 20.0;]; % in mW

CLW1 = (Power*1E6*1E-03)/(2*pi*k*L*W);

CLW1_layers = (Power*1E6*1E-03)/(2*pi*ke*L*W);

L2array = [L2; L2; L2; L2; L2+0.5; L2+0.65; L2+0.8; L2+0.9];

W2array = [W2; W2; W2; W2; W2+0.5; W2+0.65; W2+0.8; W2+0.9];

%LocationX = [0; 3; 4.5; 6; 7.5; 9; 12; 15; 18;];

%LocationY = [0; 3; 4.5; 6; 7.5; 9; 12; 15; 18;];

Thickness = [5; 10; 25; 50; 75; 100; 200; 300; 400; 500; 600;]; %in ums

xinc = 16; %Replicate sources after every 16 µm in x direction.

yinc = 13; %Replicate sources after every 13 µm in y direction.

for l=1:1

for k=5:5

for i=1:N

for j=1:N

for s = 1:array_size

for t = 1:array_size

TLW(i,j) = tempxy_layers(CLW1(k), CLW1_layers(k), s*xinc+x0, t*yinc+y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),-s*xinc+x0, t*yinc+y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),-s*xinc+x0,-t*yinc+y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),s*xinc+x0,-t*yinc+y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z);

end

end

for t = 1:array_size

TLW(i,j) = TLW(i,j) + tempxy_layers(CLW1(k), CLW1_layers(k), 0+x0,t*yinc+y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),0+x0,-t*yinc+y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z);

end

for s = 1:array_size

TLW(i,j) = TLW(i,j) + tempxy_layers(CLW1(k), CLW1_layers(k), s*xinc+x0, 0+y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z) + ...

tempxy_layers(CLW1(k),CLW1_layers(k),-s*xinc+x0, 0+y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z);

end

TLW(i,j) = TLW(i,j) + tempxy_layers(CLW1(k), CLW1_layers(k), x0, y0, X(i), Y(j), L2, W2, Thickness(l), k, He, ke, T0, n, z);

end

end

Thickness(l)

avg_temp(l) = avgtemp(TLW,X,Y,L2array(k),W2array(k),N)

peak_temp(l)= max(max(TLW))

end

end

% Filename : avgtemp.m


% This function is called by hbt7.m and other top level programs and calculates


% the average temperature.


function average = avgtemp(TLW,X,Y,L2,W2,N)

avg_temp = 0;

no_of_points = 0;

for i=1:N

for j=1:N

if ((abs(X(i)) < (L2)) & (abs(Y(j)) < (W2)))

avg_temp = avg_temp + TLW (j,i);

no_of_points = no_of_points + 1;

end

end

end

average = avg_temp/no_of_points;

% Filename : tempxy_layers.m


% This function is called by hbt7.m and other top level programs and


% calculates the temperature at a point (X,Y) according to given formulae.


function txy = tempxy_layers(CLW, CLW_layers, x0, y0, x1, y1, L2, W2, H, k, He, ke,T0,n,z)

% Calculate TLW

x = abs(x1-x0);

y = abs(y1-y0);

r = sqrt(x^2+y^2+z^2);

r_layers = sqrt(x^2+y^2);

exp1 = x + L2;

exp2 = x - L2;

exp3 = y + W2;

exp4 = y - W2;

exp5 = sqrt(exp1^2 + exp3^2);

exp6 = sqrt(exp2^2 + exp3^2);

exp7 = sqrt(exp2^2 + exp4^2);

exp8 = sqrt(exp1^2 + exp4^2);

line1 = exp1*log((exp3+exp5)/(exp4+exp8));

line2 = exp2*log((exp3+exp6)/(exp4+exp7));

line3 = exp3*log((exp1+exp5)/(exp2+exp6));

line4 = exp4*log((exp1+exp8)/(exp2+exp7));

txy1 = CLW_layers*(line1 - line2 + line3 - line4)*(exp(-r_layers/ ((((( k/ke)^0.25 )*H)+He))))*(1 - (exp((-r_layers*He)/((((k/ke)^0.5)*H*(H+He))))));

txy2 = CLW*(line1 - line2 + line3 - line4)*exp(-r/H);

txy3 = T0*((((((n+1)*(txy2+T0))/T0) -n)^(1/(n+1))) -1);

txy = txy3;

APPENDIX D

# Filename: fullchip.sim


# This file contains the routine to boot up F-RISC/G and


# reset the processor.


set simparms timescale 1

set trace mode tabular

set output fullchip.txt

load [nle]iddpcore_v3_flat

load [sim]fullchip_caps

vector Z_IBUS[63:0] IBUS[63] IBUS[62] IBUS[61] IBUS[60] IBUS[59] -

IBUS[58] IBUS[57] IBUS[56] IBUS[55] IBUS[54] IBUS[53] IBUS[52] IBUS[51] -

IBUS[50] IBUS[49] IBUS[48] IBUS[47] IBUS[46] IBUS[45] IBUS[44] IBUS[43] -

IBUS[42] IBUS[41] IBUS[40] IBUS[39] IBUS[38] IBUS[37] IBUS[36] IBUS[35] -

IBUS[34] IBUS[33] IBUS[32] IBUS[31] IBUS[30] IBUS[29] IBUS[28] IBUS[27] -

IBUS[26] IBUS[25] IBUS[24] IBUS[23] IBUS[22] IBUS[21] IBUS[20] IBUS[19] -

IBUS[18] IBUS[17] IBUS[16] IBUS[15] IBUS[14] IBUS[13] IBUS[12] IBUS[11] -

IBUS[10] IBUS[9] IBUS[8] IBUS[7] IBUS[6] IBUS[5] IBUS[4] IBUS[3] -

IBUS[2] IBUS[1] IBUS[0]

vector ZIBUS[31:0] IBUS[63] IBUS[61] IBUS[59] IBUS[57] IBUS[55] -

IBUS[53] IBUS[51] IBUS[49] IBUS[47] IBUS[45] IBUS[43] -

IBUS[41] IBUS[39] IBUS[37] IBUS[35] IBUS[33] -

IBUS[31] IBUS[29] IBUS[27] IBUS[25] IBUS[23] -

IBUS[21] IBUS[19] IBUS[17] IBUS[15] IBUS[13] -

IBUS[11] IBUS[9] IBUS[7] IBUS[5] IBUS[3] IBUS[1]

vector Z_IBUSLAT[63:0] ID.DEEX[9] ID.DEEX[8] ID.DEEX[7] -

ID.DEEX[6] ID.DEEX[5] ID.DEEX[4] ID.DEEX[3] ID.DEEX[2] ID.DEEX[1] -

ID.DEEX[0] ID.DE.INST1[53] ID.DE.INST1[52] ID.DE.INST1[51] -

ID.DE.INST1[50] ID.DE.INST1[49] ID.DE.INST1[48] -

ID.DEEX[29] ID.DEEX[28] ID.DEEX[27] ID.DEEX[26] ID.DEEX[25] -

ID.DEEX[24] ID.DEEX[23] ID.DEEX[22] ID.DEEX[21] ID.DEEX[20] ID.DEEX[19] -

ID.DEEX[18] ID.DEEX[17] ID.DEEX[16] ID.DEEX[15] ID.DEEX[14] ID.DEEX[13] -

ID.DEEX[12] ID.DEEX[11] ID.DEEX[10] ID.DE.INST1[27] ID.DE.INST1[26] -

ID.DE.INST1[25] ID.DE.INST1[24] ID.DE.INST1[23] ID.DE.INST1[22] -

ID.DE.INST1[21] ID.DE.INST1[20] ID.DE.INST1[19] ID.DE.INST1[18] -

ID.DE.INST1[17] ID.DE.INST1[16] ID.DE.INST1[15] ID.DE.INST1[14]

ID.DE.INST1[13] ID.DE.INST1[12] ID.DE.INST1[11] ID.DE.INST1[10] -

ID.DE.INST1[9] ID.DE.INST1[8] ID.DE.INST1[7] -

ID.DE.INST1[6] ID.DE.INST1[5] ID.DE.INST1[4] -

ID.DE.INST1[3] ID.DE.INST1[2] ID.DE.INST1[1] ID.DE.INST1[0]

vector ZIBUSLAT[31:0] ID.DEEX[9] ID.DEEX[7] ID.DEEX[5] ID.DEEX[3] -

ID.DEEX[1] ID.DE.INST1[53] ID.DE.INST1[51] ID.DE.INST1[49] ID.DEEX[29] -

ID.DEEX[27] ID.DEEX[25] ID.DEEX[21] ID.DEEX[19] -

ID.DEEX[17] ID.DEEX[15] ID.DEEX[13] ID.DEEX[11] -

ID.DE.INST1[27] ID.DE.INST1[25] ID.DE.INST1[23] -

DE.INST1[17] ID.DE.INST1[15] ID.DE.INST1[13] ID.DE.INST1[11] -

ID.DE.INST1[9] ID.DE.INST1[7] ID.DE.INST1[5] -

ID.DE.INST1[3] ID.DE.INST1[1]

vector ZABUS[31:0] ABUS[63] ABUS[61] ABUS[59] ABUS[57] ABUS[55] -

ABUS[53] ABUS[51] ABUS[49] ABUS[47] ABUS[45] ABUS[43] ABUS[41] -

ABUS[39] ABUS[37] ABUS[35] ABUS[33] ABUS[31] ABUS[29] ABUS[27] -

ABUS[25] ABUS[23] ABUS[21] ABUS[19] ABUS[17] ABUS[15] ABUS[13] -

ABUS[11] ABUS[9] ABUS[7] ABUS[5] ABUS[3] ABUS[1]

vector ZDBUSO[31:0] DBUSO[63] DBUSO[61] DBUSO[59] DBUSO[57] -

DBUSO[55] DBUSO[53] DBUSO[51] DBUSO[49] DBUSO[47] DBUSO[45] -

DBUSO[43] - DBUSO[41] DBUSO[39] DBUSO[37] DBUSO[35] DBUSO[33] -

DBUSO[31] DBUSO[29] DBUSO[27] DBUSO[25] DBUSO[23] -

DBUSO[21] DBUSO[19] DBUSO[17] DBUSO[15] DBUSO[13] -

DBUSO[11] DBUSO[9] DBUSO[7] DBUSO[5] DBUSO[3] DBUSO[1]

vector ZDBUSI[31:0] DBUSI[63] DBUSI[61] DBUSI[59] DBUSI[57] DBUSI[55] -

DBUSI[53] DBUSI[51] DBUSI[49] DBUSI[47] DBUSI[45] DBUSI[43] -

DBUSI[41] DBUSI[39] DBUSI[37] DBUSI[35] DBUSI[33] -

DBUSI[31] DBUSI[29] DBUSI[27] DBUSI[25] DBUSI[23] -

DBUSI[21] DBUSI[19] DBUSI[17] DBUSI[15] DBUSI[13] -

DBUSI[11] DBUSI[9] DBUSI[7] DBUSI[5] DBUSI[3] DBUSI[1]

vector IDCC[3:0] CC[7] CC[5] CC[3] CC[1]

vector ZDP3CC[3:0] DP3CC[7] DP3CC[5] DP3CC[3] DP3CC[1]

vector IDPHCLK[4:1] ID.CLKGEN.PH4.P2[1] ID.CLKGEN.PH4.P3[1] -ID.CLKGEN.PH4.P4[1] ID.CLKGEN.PH4.P1[1]

vector DP0PHCLK[4:1] DP0.CLKTREE.PH4.P2[1] DP0.CLKTREE.PH4.P3[1] DP0.CLKTREE.PH4.P4[1] DP0.CLKTREE.PH4.P1[1]

vector DP1PHCLK[4:1] DP1.CLKTREE.PH4.P2[1] DP1.CLKTREE.PH4.P3[1] DP1.CLKTREE.PH4.P4[1] DP1.CLKTREE.PH4.P1[1]

vector DP2PHCLK[4:1] DP2.CLKTREE.PH4.P2[1] DP2.CLKTREE.PH4.P3[1] DP2.CLKTREE.PH4.P4[1] DP2.CLKTREE.PH4.P1[1]

vector DP3PHCLK[4:1] DP3.CLKTREE.PH4.P2[1] DP3.CLKTREE.PH4.P3[1] DP3.CLKTREE.PH4.P4[1] DP3.CLKTREE.PH4.P1[1]

vector SYNCB[1:0] SYNC[1] SYNC[0]

vector RESETB[1:0] RESET[1] RESET[0]

vector IDINPSEL[1:0] IDINP_SEL[1] IDINP_SEL[0]

vector DP0INPSEL[1:0] DP0INP_SEL[1] DP0INP_SEL[0]

vector DP1INPSEL[1:0] DP1INP_SEL[1] DP1INP_SEL[0]

vector DP2INPSEL[1:0] DP2INP_SEL[1] DP2INP_SEL[0]

vector DP3INPSEL[1:0] DP3INP_SEL[1] DP3INP_SEL[0]

vector IDTESTB[1:0] IDTEST[1] IDTEST[0]

vector DP0TESTB[1:0] DP0TEST[1] DP0TEST[0]

vector DP1TESTB[1:0] DP1TEST[1] DP1TEST[0]

vector DP2TESTB[1:0] DP2TEST[1] DP2TEST[0]

vector DP3TESTB[1:0] DP3TEST[1] DP3TEST[0]

vector MISSIB[1:0] IDMISSI[1] IDMISSI[0]

vector MISSDB[1:0] IDMISSD[1] IDMISSD[0]

vector TRAPIB[1:0] IDTRAPI[1] IDTRAPI[0]

vector TRAPDB[1:0] IDTRAPD[1] IDTRAPD[0]

vector ERRORB[1:0] IDERROR[1] IDERROR[0]

vector INTB[1:0] IDINT[1] IDINT[0]

vector INTUB[1:0] IDINTU[1] IDINTU[0]

vector INTDISB[1:0] IDINTDIS[1] IDINTDIS[0]

vector ZCARRY[5:0] DP3COUT[1] DP3CIN[1] DP2CIN[1] DP1CIN[1] DP0CIN[1]-IDCINLSS[1]

vector ZFLUSH[4:0] DP3FLUSH[1] DP2FLUSH[1] DP1FLUSH[1] DP0FLUSH[1]-

FLUSH[1]

vector ZFLUSHDP[4:0] DP3FLUSHDP[1] DP2FLUSHDP[1] DP1FLUSHDP[1]-

DP0FLUSHDP[1] FLUSHDP[1]

vector ZSTALL[4:0] DP3STALL[1] DP2STALL[1] DP1STALL[1] DP0STALL[1] -

STALL[1]

vector ZWPSW[4:0] DP3WPSW[1] DP2WPSW[1] DP1WPSW[1] DP0WPSW[1] -

WPSW[1]

vector ZZOUT[2:0] DP2ZOUT[1] DP1ZOUT[1] DP0ZOUT[1]

vector ZZIN[2:0] DP3ZIN0[1] DP3ZIN1[1] DP3ZIN2[1]

vector ZSHIFTH[3:0] DP0SHIFTH[1] DP1SHIFTH[1] DP2SHIFTH[1] - DP3SHIFTH[1]

vector ZIMMSEL[4:0] DP3IMMSEL[1] DP2IMMSEL[1] DP1IMMSEL[1] DP0IMMSEL[1] IMMSEL[1]

vector IMMID[15:0] IMM[31] IMM[29] IMM[27] IMM[25] IMM[23] IMM[21] -IMM[19] IMM[17] IMM[15] IMM[13] IMM[11] IMM[9] IMM[7] IMM[5]-

IMM[3] IMM[1]

vector IMMDP0[7:0] DP0IMM[15] DP0IMM[13] DP0IMM[11] DP0IMM[9] -

DP0IMM[7] DP0IMM[5] DP0IMM[3] DP0IMM[1]

vector IMMDP1[7:0] DP1IMM[15] DP1IMM[13] DP1IMM[11] DP1IMM[9]-

DP1IMM[7] DP1IMM[5] DP1IMM[3] DP1IMM[1]

vector IMMDP2[7:0] DP2IMM[15] DP2IMM[13] DP2IMM[11] DP2IMM[9] -

DP2IMM[7] DP2IMM[5] DP2IMM[3] DP2IMM[1]

vector IMMDP3[7:0] DP3IMM[15] DP3IMM[13] DP3IMM[11] DP3IMM[9] -

DP3IMM[7] DP3IMM[5] DP3IMM[3] DP3IMM[1]

vector ZBRA[5:0] DP3BRAOUT2[1] IDBRA[1] DP3BRAOUT[1] DP2BRAIN[1] -

DP1BRAIN[1] DP0BRAIN[1]

vector ZALUOPH[4:0] DP3ALUOPH[1] DP2ALUOPH[1] DP1ALUOPH[1] -

DP0ALUOPH[1] ALUOPH[1]

vector ZALUOPL[4:0] DP3ALUOPL[1] DP2ALUOPL[1] DP1ALUOPL[1] -

DP0ALUOPL[1] ALUOPL[1]

vector ZINVB[4:0] DP3INVB[1] DP2INVB[1] DP1INVB[1] DP0INVB[1] INVB[1]

vector ZSCC[4:0] DP3SCC[1] DP2SCC[1] DP1SCC[1] DP0SCC[1] SCC[1]

vector ZOPAH[4:0] DP3OPAH[1] DP2OPAH[1] DP1OPAH[1] DP0OPAH[1] -

OPAH[1]

vector ZOPAL[4:0] DP3OPAL[1] DP2OPAL[1] DP1OPAL[1] DP0OPAL[1] OPAL[1]

vector ZOPBL[4:0] DP3OPBL[1] DP2OPBL[1] DP1OPBL[1] DP0OPBL[1] OPBL[1]

vector ZFFRAH[4:0] DP3FFRAH[1] DP2FFRAH[1] DP1FFRAH[1] DP0FFRAH[1] -

FFRAH[1]

vector ZFFRAL[4:0] DP3FFRAL[1] DP2FFRAL[1] DP1FFRAL[1] DP0FFRAL[1] FFRAL[1]

vector ZFFRBH[4:0] DP3FFRBH[1] DP2FFRBH[1] DP1FFRBH[1] DP0FFRBH[1] FFRBH[1]

vector ZFFRBL[4:0] DP3FFRBL[1] DP2FFRBL[1] DP1FFRBL[1] DP0FFRBL[1] -

FFRBL[1]

vector ZMBYA[4:0] DP3MBYA[1] DP2MBYA[1] DP1MBYA[1] DP0MBYA[1] -

MBYA[1]

vector ZMBYB[4:0] DP3MBYB[1] DP2MBYB[1] DP1MBYB[1] DP0MBYB[1] -

MBYB[1]

vector ZWDOUT[4:0] DP3WDOUT[1] DP2WDOUT[1] DP1WDOUT[1] -DP0WDOUT[1] WDOUT[1]

vector ZRESSEL[4:0] DP3RESSEL[1] DP2RESSEL[1] DP1RESSEL[1] DP0RESSEL[1] RESSEL[1]

vector ZRFWR[4:0] DP3RFWR[1] DP2RFWR[1] DP1RFWR[1] DP0RFWR[1] RFWR[1]

vector ZSPECIAL[4:0] DP3SPECIAL[1] DP2SPECIAL[1] DP1SPECIAL[1] DP0SPECIAL[1] SPECIAL[1]

vector ZPCLOCK[4:0] DP3PCLOCK[1] DP2PCLOCK[1] DP1PCLOCK[1] DP0PCLOCK[1] PCLOCK[1]

vector ZRFSEL[4:0] DP3RFSEL[1] DP2RFSEL[1] DP1RFSEL[1] DP0RFSEL[1] RFSEL[1]

vector PCI1[31:0] DP3.PCS.PC_I1[15] DP3.PCS.PC_I1[13] DP3.PCS.PC_I1[11] -

DP3.PCS.PC_I1[9] DP3.PCS.PC_I1[7] DP3.PCS.PC_I1[5] DP3.PCS.PC_I1[3] -

DP3.PCS.PC_I1[1] DP2.PCS.PC_I1[15] DP2.PCS.PC_I1[13] DP2.PCS.PC_I1[11] -

DP2.PCS.PC_I1[9] DP2.PCS.PC_I1[7] DP2.PCS.PC_I1[5] DP2.PCS.PC_I1[3] -

DP2.PCS.PC_I1[1] DP1.PCS.PC_I1[15] DP1.PCS.PC_I1[13] DP1.PCS.PC_I1[11] -

DP1.PCS.PC_I1[9] DP1.PCS.PC_I1[7] DP1.PCS.PC_I1[5] DP1.PCS.PC_I1[3]-

DP1.PCS.PC_I1[1] DP0.PCS.PC_I1[15] DP0.PCS.PC_I1[13] DP0.PCS.PC_I1[11] -

DP0.PCS.PC_I1[9] DP0.PCS.PC_I1[7] DP0.PCS.PC_I1[5] -

DP0.PCS.PC_I1[3] DP0.PCS.PC_I1[1]

vector PCI2[31:0] DP3.PCS.HIST3.PCI2[3] DP3.PCS.HIST3.PCI2[1] -

DP3.PCS.HIST2.PCI2[3] DP3.PCS.HIST2.PCI2[1] DP3.PCS.HIST1.PCI2[3] -

DP3.PCS.HIST1.PCI2[1] DP3.PCS.HIST0.PCI2[3] DP3.PCS.HIST0.PCI2[1] -

DP2.PCS.HIST3.PCI2[3] DP2.PCS.HIST3.PCI2[1] DP2.PCS.HIST1.PCI2[3] -DP2.PCS.HIST1.PCI2[1] DP2.PCS.HIST0.PCI2[3] DP2.PCS.HIST0.PCI2[1] -

DP1.PCS.HIST3.PCI2[3] DP1.PCS.HIST3.PCI2[1] DP1.PCS.HIST2.PCI2[3] -DP1.PCS.HIST2.PCI2[1] DP1.PCS.HIST1.PCI2[3] DP1.PCS.HIST1.PCI2[1] -

DP1.PCS.HIST0.PCI2[3] DP1.PCS.HIST0.PCI2[1] DP0.PCS.HIST1.PCI2[3] -DP0.PCS.HIST1.PCI2[1] DP0.PCS.HIST0.PCI2[3] DP0.PCS.HIST0.PCI2[1]

vector PCDE[31:0] DP3.PC1[15] DP3.PC1[13] DP3.PC1[11] DP3.PC1[9] -

DP3.PC1[7] DP3.PC1[5] DP3.PC1[3] DP3.PC1[1] DP2.PC1[15] DP2.PC1[13] -

DP2.PC1[11]- DP2.PC1[9] DP2.PC1[7] DP2.PC1[5] DP2.PC1[3] DP2.PC1[1] -

DP1.PC1[15] DP1.PC1[13] DP1.PC1[11] DP1.PC1[9] DP1.PC1[7] DP1.PC1[5] -DP1.PC1[3] DP1.PC1[1]DP0.PC1[15] DP0.PC1[13] DP0.PC1[11] DP0.PC1[9] DP0.PC1[7] DP0.PC1[5] DP0.PC1[3] DP0.PC1[1]

vector PCEX[31:0] DP3.PCS.HIST3.EX$1.Z1[1] DP3.PCS.HIST3.EX$0.Z1[1] -

DP3.PCS.HIST2.EX$1.Z1[1] DP3.PCS.HIST2.EX$0.Z1[1] -

DP3.PCS.HIST1.EX$1.Z1[1] DP3.PCS.HIST1.EX$0.Z1[1] -

DP3.PCS.HIST0.EX$1.Z1[1] DP3.PCS.HIST0.EX$0.Z1[1] -

DP2.PCS.HIST3.EX$1.Z1[1] DP2.PCS.HIST3.EX$0.Z1[1] -

DP2.PCS.HIST2.EX$1.Z1[1] DP2.PCS.HIST2.EX$0.Z1[1] -

DP2.PCS.HIST1.EX$1.Z1[1] DP2.PCS.HIST1.EX$0.Z1[1] -

DP2.PCS.HIST0.EX$1.Z1[1] DP2.PCS.HIST0.EX$0.Z1[1] -

DP1.PCS.HIST3.EX$1.Z1[1] DP1.PCS.HIST3.EX$0.Z1[1] -

DP1.PCS.HIST2.EX$1.Z1[1] DP1.PCS.HIST2.EX$0.Z1[1] -

DP1.PCS.HIST1.EX$1.Z1[1] DP1.PCS.HIST1.EX$0.Z1[1] -

DP1.PCS.HIST0.EX$1.Z1[1] DP1.PCS.HIST0.EX$0.Z1[1] -

DP0.PCS.HIST3.EX$1.Z1[1] DP0.PCS.HIST3.EX$0.Z1[1] -

DP0.PCS.HIST2.EX$1.Z1[1] DP0.PCS.HIST2.EX$0.Z1[1] -

DP0.PCS.HIST1.EX$1.Z1[1] DP0.PCS.HIST1.EX$0.Z1[1] -

DP0.PCS.HIST0.EX$1.Z1[1] DP0.PCS.HIST0.EX$0.Z1[1]

vector PCD1[31:0] DP3.PCS.HIST3.D1$1.Z1[1] DP3.PCS.HIST3.D1$0.Z1[1] -

DP3.PCS.HIST2.D1$1.Z1[1] DP3.PCS.HIST2.D1$0.Z1[1] -

DP3.PCS.HIST1.D1$1.Z1[1] DP3.PCS.HIST1.D1$0.Z1[1] -

DP3.PCS.HIST0.D1$1.Z1[1] DP3.PCS.HIST0.D1$0.Z1[1] -

DP2.PCS.HIST3.D1$1.Z1[1] DP2.PCS.HIST3.D1$0.Z1[1] -

DP2.PCS.HIST2.D1$1.Z1[1] DP2.PCS.HIST2.D1$0.Z1[1] -

DP2.PCS.HIST1.D1$1.Z1[1] DP2.PCS.HIST1.D1$0.Z1[1] -

DP2.PCS.HIST0.D1$1.Z1[1] DP2.PCS.HIST0.D1$0.Z1[1] -

DP1.PCS.HIST3.D1$1.Z1[1] DP1.PCS.HIST3.D1$0.Z1[1] -

DP1.PCS.HIST2.D1$1.Z1[1] DP1.PCS.HIST2.D1$0.Z1[1] -

DP1.PCS.HIST1.D1$1.Z1[1] DP1.PCS.HIST1.D1$0.Z1[1] -

DP1.PCS.HIST0.D1$1.Z1[1] DP1.PCS.HIST0.D1$0.Z1[1] -

DP0.PCS.HIST3.D1$1.Z1[1] DP0.PCS.HIST3.D1$0.Z1[1] -

DP0.PCS.HIST2.D1$1.Z1[1] DP0.PCS.HIST2.D1$0.Z1[1] -

DP0.PCS.HIST1.D1$1.Z1[1] DP0.PCS.HIST1.D1$0.Z1[1] -

DP0.PCS.HIST0.D1$1.Z1[1] DP0.PCS.HIST0.D1$0.Z1[1]

vector PCD2[31:0] DP3.PCS.HIST3.D2$1.Z1[1] DP3.PCS.HIST3.D2$0.Z1[1] -

DP3.PCS.HIST2.D2$1.Z1[1] DP3.PCS.HIST2.D2$0.Z1[1] -

DP3.PCS.HIST1.D2$1.Z1[1] DP3.PCS.HIST1.D2$0.Z1[1] -

DP3.PCS.HIST0.D2$1.Z1[1] DP3.PCS.HIST0.D2$0.Z1[1] -

DP2.PCS.HIST3.D2$1.Z1[1] DP2.PCS.HIST3.D2$0.Z1[1] -

DP2.PCS.HIST2.D2$1.Z1[1] DP2.PCS.HIST2.D2$0.Z1[1] -

DP2.PCS.HIST1.D2$1.Z1[1] DP2.PCS.HIST1.D2$0.Z1[1] -

DP2.PCS.HIST0.D2$1.Z1[1] DP2.PCS.HIST0.D2$0.Z1[1] -

DP1.PCS.HIST3.D2$1.Z1[1] DP1.PCS.HIST3.D2$0.Z1[1] -

DP1.PCS.HIST2.D2$1.Z1[1] DP1.PCS.HIST2.D2$0.Z1[1] -

DP1.PCS.HIST1.D2$1.Z1[1] DP1.PCS.HIST1.D2$0.Z1[1] -

DP1.PCS.HIST0.D2$1.Z1[1] DP1.PCS.HIST0.D2$0.Z1[1] -

DP0.PCS.HIST3.D2$1.Z1[1] DP0.PCS.HIST3.D2$0.Z1[1] -

DP0.PCS.HIST2.D2$1.Z1[1] DP0.PCS.HIST2.D2$0.Z1[1] -

DP0.PCS.HIST1.D2$1.Z1[1] DP0.PCS.HIST1.D2$0.Z1[1] -

DP0.PCS.HIST0.D2$1.Z1[1] DP0.PCS.HIST0.D2$0.Z1[1]

vector PCDW[31:0] DP3.PCDW[15] DP3.PCDW[13] DP3.PCDW[11] DP3.PCDW[9] DP3.PCDW[7] DP3.PCDW[5] DP3.PCDW[3] DP3.PCDW[1] -

DP2.PCDW[15] DP2.PCDW[13] DP2.PCDW[11] DP2.PCDW[9] DP2.PCDW[7] DP2.PCDW[5] DP2.PCDW[3] DP2.PCDW[1] -

DP1.PCDW[15] DP1.PCDW[13] DP1.PCDW[11] DP1.PCDW[9] DP1.PCDW[7] DP1.PCDW[5] DP1.PCDW[3] DP1.PCDW[1] -

DP0.PCDW[15] DP0.PCDW[13] DP0.PCDW[11] DP0.PCDW[9] DP0.PCDW[7] DP0.PCDW[5] DP0.PCDW[3] DP0.PCDW[1]

vector PCINC[31:0] DP3.PCS.PCI1.INC_OUT1[15] DP3.PCS.PCI1.INC_OUT1[13] -

DP3.PCS.PCI1.INC_OUT1[11] DP3.PCS.PCI1.INC_OUT1[9] DP3.PCS.PCI1.INC_OUT1[7] -

DP3.PCS.PCI1.INC_OUT1[5] DP3.PCS.PCI1.INC_OUT1[3] DP3.PCS.PCI1.INC_OUT1[1] -

DP2.PCS.PCI1.INC_OUT1[15] DP2.PCS.PCI1.INC_OUT1[13] -

DP2.PCS.PCI1.INC_OUT1[11] DP2.PCS.PCI1.INC_OUT1[9] DP2.PCS.PCI1.INC_OUT1[7] -

DP2.PCS.PCI1.INC_OUT1[5] DP2.PCS.PCI1.INC_OUT1[3] DP2.PCS.PCI1.INC_OUT1[1] -

DP1.PCS.PCI1.INC_OUT1[15] DP1.PCS.PCI1.INC_OUT1[13] -

DP1.PCS.PCI1.INC_OUT1[11] DP1.PCS.PCI1.INC_OUT1[9] DP1.PCS.PCI1.INC_OUT1[7] -

DP1.PCS.PCI1.INC_OUT1[5] DP1.PCS.PCI1.INC_OUT1[3] DP1.PCS.PCI1.INC_OUT1[1] -

DP0.PCS.PCI1.INC_OUT1[15] DP0.PCS.PCI1.INC_OUT1[13] -

DP0.PCS.PCI1.INC_OUT1[11] DP0.PCS.PCI1.INC_OUT1[9] DP0.PCS.PCI1.INC_OUT1[7] -

DP0.PCS.PCI1.INC_OUT1[5] DP0.PCS.PCI1.INC_OUT1[3] DP0.PCS.PCI1.INC_OUT1[1]

set radix 16 IDCC ZDP3CC ZIBUS ZIBUSLAT ZABUS ZDBUSI ZDBUSO IMMID IMMDP0 IMMDP1 IMMDP2 IMMDP3

set radix 16 ZBRA ZFFRAH ZFFRAL ZFFRBH ZFFRBL ZMBYA ZMBYB ZWDOUT ZRESSEL ZRFSEL ZRFWR ZSPECIAL ZSTALL

set radix 16 ZPCLOCK ZIMMSEL ZFLUSH ZFLUSHDP ZOPAH ZOPAL ZOPBL ZINVB ZSCC ZALUOPH ZALUOPL

set radix 16 ZWPSW ZWDOUT

set radix 16 PCINC PCI1 PCI2 PCDE PCEX PCD1 PCD2 PCDW

set alias seepcs view PCINC PCI1 PCI2 PCDE PCEX PCD1 PCD2 PCDW

set clock CLK[1] 1(250) 0(250)

set clock CLK[0] 0(250) 1(250)

# set configuration bits for DP chips

l DP0CONFH[1]

h DP0CONFH[0]

l DP0CONFL[1]

h DP0CONFL[0]

l DP1CONFH[1]

h DP1CONFH[0]

h DP1CONFL[1]

l DP1CONFL[0]

h DP2CONFH[1]

l DP2CONFH[0]

l DP2CONFL[1]

h DP2CONFL[0]

h DP3CONFH[1]

l DP3CONFH[0]

h DP3CONFL[1]

l DP3CONFL[0]

# Power up the register files on all the DP chips

h DP0.RF.RF.RFP

h DP1.RF.RF.RFP

h DP2.RF.RF.RFP

h DP3.RF.RF.RFP

watch (DISPLAY) CLK[1] SYNC[1] RESET[1] DP0PHCLK ZIBUS ZIBUSLAT -

IDCC ZDP3CC ZBRA IMMID IMMDP0 IMMDP1 IMMDP2 IMMDP3 PROT[1] -

ZALUOPH ZALUOPL ZINVB ZSCC ZOPAH ZOPAL ZOPBL ZFFRAH ZFFRAL -

ZFFRBH ZFFRBL -

ZMBYA ZMBYB ZWDOUT ZRESSEL ZRFSEL ZRFWR ZPCLOCK -

ZIMMSEL ZFLUSH ZFLUSHDP ZSTALL ZABUS ZCARRY ZSPECIAL -

ZWPSW ZWDOUT

# Set the INP_SEL and TEST signals to take input from pads

sv IDINPSEL 'b01

sv DP0INPSEL 'b01

sv DP1INPSEL 'b01

sv DP2INPSEL 'b01

sv DP3INPSEL 'b01

sv IDTESTB 'b01

sv DP0TESTB 'b01

sv DP1TESTB 'b01

sv DP2TESTB 'b01

sv DP3TESTB 'b01

sv RESETB 'b01 ERRORB 'b01 INTB 'b01 INTUB 'b01

sv MISSIB 'b01 MISSDB 'b01 TRAPIB 'b01 TRAPDB 'b01

sv SYNCB 'b01

step 100

#move to P1

sv SYNCB 'b10

step 150

#move to P2

step 250

#move to P3

step 250

#move to P4

step 250

#move to P1

step 100

# Delay added to move inputs back 1 phase

step 276

# Boot up vectors start on new P1

sv RESETB 'b01 ERRORB 'b01 INTB 'b01 INTUB 'b01

sv MISSIB 'b01 MISSDB 'b01 TRAPIB 'b01 TRAPDB 'b01

step 1000

echo ************** sv RESETB 'b10 at T = 2376 *************

sv RESETB 'b10

step 8000

echo ******** 8 ns elapsed (END of RESET)*********************

echo *************************** sv RESET 'b01 at T = 10376

sv RESETB 'b01

echo ***************************** cycle 1 *************************

step 900

# sv Z_IBUS 'h5555555555555555

step 100

seepcs

echo ***************************** cycle 2 **************

step 900

# sv Z_IBUS 'h5555555555555555

step 100

seepcs

echo ***************************** cycle 3 **************

step 900

# sv Z_IBUS 'h5555555555555555

step 100

seepcs

echo Load [sim] cout

load [sim]cout

APPENDIX E

MCM Level Schematics

Figure E.1: Deskew chip.

Figure E.2: Cache memory chip.

Figure E.3: Datapath chip.

Figure E.4: Cache controller chip.

Figure E.5: Instruction decoder chip.

Figure E.6: Top schematic - part1.

Figure E.7: Top schematic - part2.

Figure E.8: Top schematic - part3.

Figure E.9: Top schematic - part4.

Figure E.10: Top schematic - part5.

Figure E.11: Top schematic - part6.

Figure E.12: Top schematic - part7.

Figure E.13: Top schematic - part8.

Figure E.14: Top schematic - part9.

APPENDIX F

Miniature RF Connector

APPENDIX G

MCM Net Lengths and Delays

Net NameLength [mm]Delay [ps]
ICCSTALLM[1]26.33158
ICCSTALLM[0]26.33158
DCCSTALLM[1]16.3398
DCCSTALLM[0]16.3398
IDMISSI[0]29.67178
IDMISSI[1]29.67178
IDMISSD[0]37.33224
IDMISSD[1]37.33224
ICCACKI[1]19.33116
ICCACKI[0]19.33116
DCCACKD[1]28.33170
DCCACKD[0]28.33170
ICCIOCNTRL0[1]29.33176
ICCIOCNTRL0[0]29.33176
DCCIOCNTRL0[1]15.8395
DCCIOCNTRL0[0]15.8395
ICCIOCNTRL1[1]30.00180
ICCIOCNTRL1[0]30.00180
DCCIOCNTRL1[1]16.3398
DCCIOCNTRL1[0]16.3398
DCCWDC[1]36.33218
DCCWDC[0]36.33218
DCCVDA[1]36.15216.9
DCCVDA[0]36.15216.9
IDIBUS[0]9.8359
IDIBUS[1]9.8359
IDIBUS[2]9.8359
IDIBUS[3]9.8359
IDIBUS[4]9.8359
IDIBUS[5]9.8359
IDIBUS[6]15.0090
IDIBUS[7]15.0090
IDIBUS[8]10.0060
IDIBUS[9]10.0060
IDIBUS[10]10.0060
IDIBUS[11]10.0060
IDIBUS[12]10.0060
IDIBUS[13]10.0060
IDIBUS[14]10.0060
IDIBUS[15]10.0060
IDIBUS[16]19.33116
IDIBUS[17]19.33116
IDIBUS[18]20.00120
IDIBUS[19]20.00120
IDIBUS[20]20.00120
IDIBUS[21]20.00120
IDIBUS[22]20.50123
IDIBUS[23]20.50123
IDIBUS[24]23.50141
IDIBUS[25]23.50141
IDIBUS[26]17.67106
IDIBUS[27]17.67106
IDIBUS[28]17.67106
IDIBUS[29]17.67106
IDIBUS[30]18.00108
IDIBUS[31]18.00108
IDIBUS[32]17.00102
IDIBUS[33]17.00102
IDIBUS[34]17.00102
IDIBUS[35]17.00102
IDIBUS[36]22.00132
IDIBUS[37]22.00132
IDIBUS[38]29.17175
IDIBUS[39]29.17175
IDIBUS[40]14.3386
IDIBUS[41]14.3386
IDIBUS[42]14.1785
IDIBUS[43]14.1785
IDIBUS[44]14.1785
IDIBUS[45]14.1785
IDIBUS[46]14.1785
IDIBUS[47]14.1785
IDIBUS[48]21.33128
IDIBUS[49]21.33128
IDIBUS[50]20.17121
IDIBUS[51]20.17121
IDIBUS[52]20.00120
IDIBUS[53]20.00120
IDIBUS[54]17.67106
IDIBUS[55]17.67106
IDIBUS[56]24.00144
IDIBUS[57]24.00144
IDIBUS[58]23.83143
IDIBUS[59]23.83143
IDIBUS[60]24.00144
IDIBUS[61]24.00144
IDIBUS[62]24.00144
IDIBUS[63]24.00144
DBUSI[0]26.67160
DBUSI[1]26.67160
DBUSI[2]26.33158
DBUSI[3]26.33158
DBUSI[4]26.67160
DBUSI[5]26.67160
DBUSI[6]27.67166
DBUSI[7]27.67166
DBUSI[8]29.17175
DBUSI[9]29.17175
DBUSI[10]29.17175
DBUSI[11]29.17175
DBUSI[12]29.17175
DBUSI[13]29.17175
DBUSI[14]29.17175
DBUSI[15]29.17175
DBUSI[16]23.67142
DBUSI[17]23.67142
DBUSI[18]23.67142
DBUSI[19]23.67142
DBUSI[20]23.67142
DBUSI[21]23.67142
DBUSI[22]23.67142
DBUSI[23]23.67142
DBUSI[24]28.83173
DBUSI[25]28.83173
DBUSI[26]28.83173
DBUSI[27]28.83173
DBUSI[28]29.00174
DBUSI[29]29.00174
DBUSI[30]29.00174
DBUSI[31]29.00174
DBUSI[32]22.83137
DBUSI[33]22.83137
DBUSI[34]22.83137
DBUSI[35]22.83137
DBUSI[36]22.83137
DBUSI[37]22.83137
DBUSI[38]22.83137
DBUSI[39]22.83137
DBUSI[40]30.00180
DBUSI[41]30.00180
DBUSI[42]30.00180
DBUSI[43]30.00180
DBUSI[44]30.00180
DBUSI[45]30.00180
DBUSI[46]30.00180
DBUSI[47]30.00180
DBUSI[48]9.0054
DBUSI[49]9.0054
DBUSI[50]9.0054
DBUSI[51]9.0054
DBUSI[52]9.0054
DBUSI[53]9.0054
DBUSI[54]9.0054
DBUSI[55]9.0054
DBUSI[56]26.00156
DBUSI[57]26.00156
DBUSI[58]25.00150
DBUSI[59]25.00150
DBUSI[60]25.00150
DBUSI[61]25.00150
DBUSI[62]25.00150
DBUSI[63]25.00150
DBUSO[0]27.33164
DBUSO[1]27.33164
DBUSO[2]28.67172
DBUSO[3]28.67172
DBUSO[4]28.00168
DBUSO[5]28.00168
DBUSO[6]28.33170
DBUSO[7]28.33170
DBUSO[8]29.50177
DBUSO[9]29.50177
DBUSO[10]28.50171
DBUSO[11]28.50171
DBUSO[12]28.50171
DBUSO[13]28.50171
DBUSO[14]28.50171
DBUSO[15]28.50171
DBUSO[16]25.00150
DBUSO[17]25.00150
DBUSO[18]25.00150
DBUSO[19]25.00150
DBUSO[20]25.00150
DBUSO[21]25.00150
DBUSO[22]25.00150
DBUSO[23]25.00150
DBUSO[24]30.00180
DBUSO[25]30.00180
DBUSO[26]30.00180
DBUSO[27]30.00180
DBUSO[28]30.00180
DBUSO[29]30.00180
DBUSO[30]30.00180
DBUSO[31]30.00180
DBUSO[32]23.00138
DBUSO[33]23.00138
DBUSO[34]23.00138
DBUSO[35]23.00138
DBUSO[36]23.33140
DBUSO[37]23.33140
DBUSO[38]23.33140
DBUSO[39]23.33140
DBUSO[40]29.33176
DBUSO[41]29.33176
DBUSO[42]28.33170
DBUSO[43]28.33170
DBUSO[44]28.33170
DBUSO[45]28.33170
DBUSO[46]28.00168
DBUSO[47]28.00168
DBUSO[48]8.0048
DBUSO[49]8.0048
DBUSO[50]8.0048
DBUSO[51]8.0048
DBUSO[52]10.0060
DBUSO[53]10.0060
DBUSO[54]10.0060
DBUSO[55]10.0060
DBUSO[56]24.67148
DBUSO[57]24.67148
DBUSO[58]24.00144
DBUSO[59]24.00144
DBUSO[60]24.00144
DBUSO[61]24.00144
DBUSO[62]24.00144
DBUSO[63]24.00144
DCCADR[63]23.33140
DCCADR[62]23.33140
DCCADR[61]23.50141
DCCADR[60]23.50141
DCCADR[59]23.67142
DCCADR[58]23.67142
DCCADR[57]24.67148
DCCADR[56]24.67148
DCCADR[55]25.00150
DCCADR[54]25.00150
DCCADR[53]25.00150
DCCADR[52]25.00150
DCCADR[51]25.00150
DCCADR[50]25.00150
DCCADR[49]26.00156
DCCADR[48]26.00156
DCCADR[47]14.8389
DCCADR[46]14.8389
DCCADR[45]15.0090
DCCADR[44]15.0090
DCCADR[43]15.1791
DCCADR[42]15.1791
DCCADR[41]16.3398
DCCADR[40]16.3398
DCCADR[39]16.3398
DCCADR[38]16.3398
DCCADR[37]16.0096
DCCADR[36]16.0096
DCCADR[35]16.1797
DCCADR[34]16.1797
DCCADR[33]16.67100
DCCADR[32]16.67100
DCCADR[31]12.1773
DCCADR[30]12.1773
DCCADR[29]12.0072
DCCADR[28]12.0072
DCCADR[27]11.8371
DCCADR[26]11.8371
DCCADR[25]10.8365
DCCADR[24]10.8365
DCCADR[23]10.6764
DCCADR[22]10.6764
DCCADR[21]10.5063
DCCADR[20]10.5063
DCCADR[19]10.3362
DCCADR[18]10.3362
DCCADR[17]9.6758
DCCADR[16]9.6758
DCCADR[15]20.67124
DCCADR[14]20.67124
DCCADR[13]20.17121
DCCADR[12]20.17121
DCCADR[11]20.33122
DCCADR[10]20.33122
DCCADR[9]21.33128
DCCADR[8]21.33128
DCCADR[7]21.50129
DCCADR[6]21.50129
DCCADR[5]21.67130
DCCADR[4]21.67130
DCCADR[3]22.00132
DCCADR[2]22.00132
DCCADR[1]22.50135
DCCADR[0]22.50135
ICCADR[0]12.0072
ICCADR[1]12.0072
ICCADR[2]11.6770
ICCADR[3]11.6770
ICCADR[4]11.3368
ICCADR[5]11.3368
ICCADR[6]11.1767
ICCADR[7]11.1767
ICCADR[8]11.0066
ICCADR[9]11.0066
ICCADR[10]10.0060
ICCADR[11]10.0060
ICCADR[12]9.8359
ICCADR[13]9.8359
ICCADR[14]10.3362
ICCADR[15]10.3362
ICCADR[16]20.50123
ICCADR[17]20.50123
ICCADR[18]24.67148
ICCADR[19]24.67148
ICCADR[20]24.00144
ICCADR[21]24.00144
ICCADR[22]23.83143
ICCADR[23]23.83143
ICCADR[24]23.67142
ICCADR[25]23.67142
ICCADR[26]24.50147
ICCADR[27]24.50147
ICCADR[28]24.33146
ICCADR[29]24.33146
ICCADR[30]24.00144
ICCADR[31]24.00144
ICCADR[32]30.83185
ICCADR[33]30.83185
ICCADR[34]29.33176
ICCADR[35]29.33176
ICCADR[36]29.00174
ICCADR[37]29.00174
ICCADR[38]32.00192
ICCADR[39]32.00192
ICCADR[40]31.50189
ICCADR[41]31.50189
ICCADR[42]30.17181
ICCADR[43]30.17181
ICCADR[44]30.17181
ICCADR[45]30.17181
ICCADR[46]30.00180
ICCADR[47]30.00180
ICCADR[48]40.67244
ICCADR[49]40.67244
ICCADR[50]40.50243
ICCADR[51]40.50243
ICCADR[52]40.50243
ICCADR[53]40.50243
ICCADR[54]40.83245
ICCADR[55]40.83245
ICCADR[56]41.00246
ICCADR[57]41.00246
ICCADR[58]40.00240
ICCADR[59]40.00240
ICCADR[60]34.50207
ICCADR[61]34.50207
ICCADR[62]35.67214
ICCADR[63]35.67214
DP0COUTI[0]10.0060
DP0COUTI[1]10.0060
DP0COUT[0]10.0060
DP0COUT[1]10.0060
DP1COUTI[0]10.0060
DP1COUTI[1]10.0060
DP1COUT[0]10.0060
DP1COUT[1]10.0060
DP2COUTI[0]10.0060
DP2COUTI[1]10.0060
DP2COUT[0]10.0060
DP2COUT[1]10.0060
DP3BRAIN[0]5.0030
DP3BRAIN[1]5.0030
DP3COUTI[0]10.0060
DP3COUTI[1]10.0060
DP3COUT[0]10.0060
DP3COUT[1]10.0060
DP0ALUOPH[0]8.6752
DP0ALUOPH[1]8.6752
DP0ALUOPL[0]8.7152.26
DP0ALUOPL[1]8.7152.26
DP0BRAIN[0]29.08174.45
DP0BRAIN[1]29.08174.45
DP0CIN[0]9.4356.55
DP0CIN[1]9.4356.55
DP0FFRAH[0]1.7010.2
DP0FFRAH[1]1.7010.2
DP0FFRAL[0]1.7010.2
DP0FFRAL[1]1.7010.2
DP0FFRBH[0]1.7310.35
DP0FFRBH[1]1.7310.35
DP0FFRBL[0]1.7310.35
DP0FFRBL[1]1.7310.35
DP0FLUSH[0]16.85101.1
DP0FLUSH[1]16.85101.1
DP0FLUSHDP[0]18.58111.45
DP0FLUSHDP[1]18.58111.45
DP0IMMSEL[0]10.1861.05
DP0IMMSEL[1]10.1861.05
DP0IMM[0]16.78100.65
DP0IMM[10]5.0830.45
DP0IMM[11]5.0830.45
DP0IMM[12]4.7828.65
DP0IMM[13]4.7828.65
DP0IMM[14]4.1825.05
DP0IMM[15]4.1825.05
DP0IMM[1]16.78100.65
DP0IMM[2]16.70100.2
DP0IMM[3]16.70100.2
DP0IMM[4]12.3574.1
DP0IMM[5]12.3574.1
DP0IMM[6]9.8859.25
DP0IMM[7]9.8859.25
DP0IMM[8]9.4356.55
DP0IMM[9]9.4356.55
DP0INVB[0]17.23103.35
DP0INVB[1]17.23103.35
DP0MBYA[0]1.7010.2
DP0MBYA[1]1.7010.2
DP0MBYB[0]1.7010.2
DP0MBYB[1]1.7010.2
DP0OPAH[0]17.98107.85
DP0OPAH[1]17.98107.85
DP0OPAL[0]17.98107.85
DP0OPAL[1]17.98107.85
DP0OPBL[0]17.98107.85
DP0OPBL[1]17.98107.85
DP0PCLOCK[0]2.3013.8
DP0PCLOCK[1]2.3013.8
DP0RESSEL[0]4.8629.175
DP0RESSEL[1]4.8629.175
DP0RFA_A[0]2.5015
DP0RFA_A[1]2.5015
DP0RFA_A[2]2.5015
DP0RFA_A[3]2.5015
DP0RFA_A[4]2.5015
DP0RFA_A[5]2.5015
DP0RFA_A[6]2.5015
DP0RFA_A[7]2.5015
DP0RFA_A[8]2.5015
DP0RFA_A[9]2.5015
DP0RFA_BD[0]2.5015
DP0RFA_BD[1]2.5015
DP0RFA_BD[2]2.5015
DP0RFA_BD[3]2.5015
DP0RFA_BD[4]2.5015
DP0RFA_BD[5]2.5015
DP0RFA_BD[6]2.5015
DP0RFA_BD[7]2.5015
DP0RFA_BD[8]2.5015
DP0RFA_BD[9]2.5015
DP0RFSEL[0]14.5087
DP0RFSEL[1]14.5087
DP0RFWR[0]5.3332
DP0RFWR[1]5.3332
DP0SCC[0]13.7882.65
DP0SCC[1]13.7882.65
DP0SHIFTL[0]29.23175.35
DP0SHIFTL[1]29.23175.35
DP0SPECIAL[0]16.1096.6
DP0SPECIAL[1]16.1096.6
DP0STALL[0]15.5093
DP0STALL[1]15.5093
DP0UI[0]14.6888.05
DP0UI[1]14.6888.05
DP0WDOUT[0]12.2073.2
DP0WDOUT[1]12.2073.2
DP0WPSW[0]17.33104
DP0WPSW[1]17.33104
DP1ALUOPH[0]8.9853.85
DP1ALUOPH[1]8.9853.85
DP1ALUOPL[0]8.7152.26
DP1ALUOPL[1]8.7152.26
DP1BRAIN[0]20.10120.6
DP1BRAIN[1]20.10120.6
DP1CINI[0]10.0060
DP1CINI[1]10.0060
DP1CIN[0]9.1354.75
DP1CIN[1]9.1354.75
DP1FFRAH[0]8.9853.85
DP1FFRAH[1]8.9853.85
DP1FFRAL[0]8.9853.85
DP1FFRAL[1]8.9853.85
DP1FFRBH[0]8.9853.85
DP1FFRBH[1]8.9853.85
DP1FFRBL[0]8.9853.85
DP1FFRBL[1]8.9853.85
DP1FLUSH[0]8.9853.85
DP1FLUSH[1]8.9853.85
DP1FLUSHDP[0]8.9853.85
DP1FLUSHDP[1]8.9853.85
DP1IMMSEL[0]8.9853.85
DP1IMMSEL[1]8.9853.85
DP1IMM[0]27.07162.4
DP1IMM[10]16.98101.85
DP1IMM[11]16.98101.85
DP1IMM[12]17.13102.75
DP1IMM[13]17.13102.75
DP1IMM[14]14.2885.65
DP1IMM[15]14.2885.65
DP1IMM[1]27.07162.4
DP1IMM[2]22.15132.9
DP1IMM[3]22.15132.9
DP1IMM[4]20.25121.5
DP1IMM[5]20.25121.5
DP1IMM[6]20.25121.5
DP1IMM[7]20.25121.5
DP1IMM[8]19.83118.95
DP1IMM[9]19.83118.95
DP1INP_SEL[0]20.00120
DP1INP_SEL[1]20.00120
DP1INVB[0]8.9853.85
DP1INVB[1]8.9853.85
DP1MBYA[0]8.9853.85
DP1MBYA[1]8.9853.85
DP1MBYB[0]8.9853.85
DP1MBYB[1]8.9853.85
DP1OPAH[0]8.9853.85
DP1OPAH[1]8.9853.85
DP1OPAL[0]8.9853.85
DP1OPAL[1]8.9853.85
DP1OPBL[0]8.9853.85
DP1OPBL[1]8.9853.85
DP1PCLOCK[0]8.9853.85
DP1PCLOCK[1]8.9853.85
DP1RESSEL[0]8.9853.85
DP1RESSEL[1]8.9853.85
DP1RFA_A[0]10.0060
DP1RFA_A[1]10.0060
DP1RFA_A[2]10.0060
DP1RFA_A[3]10.0060
DP1RFA_A[4]10.0060
DP1RFA_A[5]10.0060
DP1RFA_A[6]10.0060
DP1RFA_A[7]10.0060
DP1RFA_A[8]10.0060
DP1RFA_A[9]10.0060
DP1RFA_BD[0]10.0060
DP1RFA_BD[1]10.0060
DP1RFA_BD[2]10.0060
DP1RFA_BD[3]10.0060
DP1RFA_BD[4]10.0060
DP1RFA_BD[5]10.0060
DP1RFA_BD[6]10.0060
DP1RFA_BD[7]10.0060
DP1RFA_BD[8]10.0060
DP1RFA_BD[9]10.0060
DP1RFSEL[0]9.0054
DP1RFSEL[1]9.0054
DP1RFWR[0]9.0054
DP1RFWR[1]9.0054
DP1SCAN[0]20.00120
DP1SCAN[1]20.00120
DP1SCAN_IN[0]20.00120
DP1SCAN_IN[1]20.00120
DP1SCAN_OUT[0]20.00120
DP1SCAN_OUT[1]20.00120
DP1SCC[0]9.0054
DP1SCC[1]9.0054
DP1SC[0]20.00120
DP1SC[1]20.00120
DP1SEL[0]20.00120
DP1SEL[1]20.00120
DP1SHIFTL[0]9.5057
DP1SHIFTL[1]9.5057
DP1SPECIAL[0]9.0054
DP1SPECIAL[1]9.0054
DP1STALL[0]9.0054
DP1STALL[1]9.0054
DP1START[0]20.00120
DP1START[1]20.00120
DP1TEST[0]20.00120
DP1TEST[1]20.00120
DP1VIEWA20.00120
DP1VIEWB20.00120
DP1WDOUT[0]9.0054
DP1WDOUT[1]9.0054
DP1WPSW[0]9.0054
DP1WPSW[1]9.0054
DP2ALUOPH[0]8.9853.85
DP2ALUOPH[1]8.9853.85
DP2ALUOPL[0]8.7152.26
DP2ALUOPL[1]8.7152.26
DP2BRAIN[0]11.1366.75
DP2BRAIN[1]11.1366.75
DP2CINI[0]10.0060
DP2CINI[1]10.0060
DP2CIN[0]9.1354.75
DP2CIN[1]9.1354.75
DP2FFRAH[0]8.9853.85
DP2FFRAH[1]8.9853.85
DP2FFRAL[0]8.9853.85
DP2FFRAL[1]8.9853.85
DP2FFRBH[0]8.9853.85
DP2FFRBH[1]8.9853.85
DP2FFRBL[0]8.9853.85
DP2FFRBL[1]8.9853.85
DP2FLUSH[0]8.9853.85
DP2FLUSH[1]8.9853.85
DP2FLUSHDP[0]8.9853.85
DP2FLUSHDP[1]8.9853.85
DP2IMMSEL[0]8.9853.85
DP2IMMSEL[1]8.9853.85
DP2IMM[0]20.95125.7
DP2IMM[10]21.50129
DP2IMM[11]21.50129
DP2IMM[12]22.95137.7
DP2IMM[13]22.95137.7
DP2IMM[14]22.50135
DP2IMM[15]22.50135
DP2IMM[1]20.95125.7
DP2IMM[2]17.95107.7
DP2IMM[3]17.95107.7
DP2IMM[4]18.40110.4
DP2IMM[5]18.40110.4
DP2IMM[6]17.95107.7
DP2IMM[7]17.95107.7
DP2IMM[8]23.80142.8
DP2IMM[9]23.80142.8
DP2INP_SEL[0]30.00180
DP2INP_SEL[1]30.00180
DP2INVB[0]8.9853.85
DP2INVB[1]8.9853.85
DP2MBYA[0]10.9865.85
DP2MBYA[1]10.9865.85
DP2MBYB[0]10.9865.85
DP2MBYB[1]10.9865.85
DP2OPAH[0]8.9853.85
DP2OPAH[1]8.9853.85
DP2OPAL[0]8.9853.85
DP2OPAL[1]8.9853.85
DP2OPBL[0]8.9853.85
DP2OPBL[1]8.9853.85
DP2PCLOCK[0]8.9853.85
DP2PCLOCK[1]8.9853.85
DP2RESSEL[0]8.9853.85
DP2RESSEL[1]8.9853.85
DP2RFA_A[0]10.0060
DP2RFA_A[1]10.0060
DP2RFA_A[2]10.0060
DP2RFA_A[3]10.0060
DP2RFA_A[4]10.0060
DP2RFA_A[5]10.0060
DP2RFA_A[6]10.0060
DP2RFA_A[7]10.0060
DP2RFA_A[8]10.0060
DP2RFA_A[9]10.0060
DP2RFA_BD[0]10.0060
DP2RFA_BD[1]10.0060
DP2RFA_BD[2]10.0060
DP2RFA_BD[3]10.0060
DP2RFA_BD[4]10.0060
DP2RFA_BD[5]10.0060
DP2RFA_BD[6]10.0060
DP2RFA_BD[7]10.0060
DP2RFA_BD[8]10.0060
DP2RFA_BD[9]10.0060
DP2RFSEL[0]9.0054
DP2RFSEL[1]9.0054
DP2RFWR[0]9.0054
DP2RFWR[1]9.0054
DP2SCAN[0]30.00180
DP2SCAN[1]30.00180
DP2SCAN_IN[0]30.00180
DP2SCAN_IN[1]30.00180
DP2SCAN_OUT[0]30.00180
DP2SCAN_OUT[1]30.00180
DP2SCC[0]9.0054
DP2SCC[1]9.0054
DP2SC[0]30.00180
DP2SC[1]30.00180
DP2SEL[0]30.00180
DP2SEL[1]30.00180
DP2SHIFTL[0]9.5057
DP2SHIFTL[1]9.5057
DP2SPECIAL[0]9.0054
DP2SPECIAL[1]9.0054
DP2STALL[0]9.0054
DP2STALL[1]9.0054
DP2VIEWA30.00180
DP2VIEWB30.00180
DP2WDOUT[0]9.0054
DP2WDOUT[1]9.0054
DP2WPSW[0]9.0054
DP2WPSW[1]9.0054
DP3ALUOPH[0]10.9865.85
DP3ALUOPH[1]10.9865.85
DP3ALUOPL[0]10.9865.85
DP3ALUOPL[1]10.9865.85
DP3CC[0]20.00120
DP31CC[0]20.00120
DP3CC[1]20.00120
DP31CC[1]20.00120
DP3CC[2]20.00120
DP31CC[2]20.00120
DP3CC[3]20.00120
DP31CC[3]20.00120
DP3CC[4]20.00120
DP31CC[4]20.00120
DP3CC[5]20.00120
DP31CC[5]20.00120
DP3CC[6]20.00120
DP31CC[6]20.00120
DP3CC[7]20.00120
DP31CC[7]20.00120
DP3CINI[0]10.0060
DP3CINI[1]10.0060
DP3CIN[0]10.8364.95
DP3CIN[1]10.8364.95
DP3FFRAH[0]10.6864.05
DP3FFRAH[1]10.6864.05
DP3FFRAL[0]10.6864.05
DP3FFRAL[1]10.6864.05
DP3FFRBH[0]10.6864.05
DP3FFRBH[1]10.6864.05
DP3FFRBL[0]10.6864.05
DP3FFRBL[1]10.6864.05
DP3FLUSH[0]10.6864.05
DP3FLUSH[1]10.6864.05
DP3FLUSHDP[0]10.9865.85
DP3FLUSHDP[1]10.9865.85
DP3IMMSEL[0]11.2867.65
DP3IMMSEL[1]11.2867.65
DP3IMM[0]20.25121.5
DP3IMM[10]20.25121.5
DP3IMM[11]20.25121.5
DP3IMM[12]19.95119.7
DP3IMM[13]19.95119.7
DP3IMM[14]19.95119.7
DP3IMM[15]19.95119.7
DP3IMM[1]20.25121.5
DP3IMM[2]19.95119.7
DP3IMM[3]19.95119.7
DP3IMM[4]20.25121.5
DP3IMM[5]20.25121.5
DP3IMM[6]20.25121.5
DP3IMM[7]20.25121.5
DP3IMM[8]20.25121.5
DP3IMM[9]20.25121.5
DP3INP_SEL[0]10.0060
DP3INP_SEL[1]10.0060
DP3INVB[0]10.9865.85
DP3INVB[1]10.9865.85
DP3MBYA[0]10.9865.85
DP3MBYA[1]10.9865.85
DP3MBYB[0]10.9865.85
DP3MBYB[1]10.9865.85
DP3OPAH[0]11.2867.65
DP3OPAH[1]11.2867.65
DP3OPAL[0]11.2867.65
DP3OPAL[1]11.2867.65
DP3OPBL[0]11.2867.65
DP3OPBL[1]11.2867.65
DP3PCLOCK[0]10.9865.85
DP3PCLOCK[1]10.9865.85
DP3RESSEL[0]10.9865.85
DP3RESSEL[1]10.9865.85
DP3RFA_A[0]10.9865.85
DP3RFA_A[1]10.9865.85
DP3RFA_A[2]10.9865.85
DP3RFA_A[3]10.9865.85
DP3RFA_A[4]10.9865.85
DP3RFA_A[5]10.9865.85
DP3RFA_A[6]10.9865.85
DP3RFA_A[7]10.9865.85
DP3RFA_A[8]10.9865.85
DP3RFA_A[9]10.9865.85
DP3RFA_BD[0]10.9865.85
DP3RFA_BD[1]10.9865.85
DP3RFA_BD[2]10.9865.85
DP3RFA_BD[3]10.9865.85
DP3RFA_BD[4]10.9865.85
DP3RFA_BD[5]10.9865.85
DP3RFA_BD[6]10.9865.85
DP3RFA_BD[7]10.9865.85
DP3RFA_BD[8]10.9865.85
DP3RFA_BD[9]10.9865.85
DP3RFSEL[0]10.9865.85
DP3RFSEL[1]10.9865.85
DP3RFWR[0]10.9865.85
DP3RFWR[1]10.9865.85
DP3SCAN[0]10.0060
DP3SCAN[1]10.0060
DP3SCAN_IN[0]10.0060
DP3SCAN_IN[1]10.0060
DP3SCAN_OUT[0]10.0060
DP3SCAN_OUT[1]10.0060
DP3SCC[0]11.0066
DP3SCC[1]11.0066
DP3SC[0]10.0060
DP3SC[1]10.0060
DP3SEL[0]10.0060
DP3SEL[1]10.0060
DP3SHIFTL[0]11.5069
DP3SHIFTL[1]11.5069
DP3SPECIAL[0]11.3368
DP3SPECIAL[1]11.3368
DP3STALL[0]11.3368
DP3STALL[1]11.3368
DP3START[0]10.0060
DP3START[1]10.0060
DP3TEST[0]10.0060
DP3TEST[1]10.0060
DP3VIEWA10.0060
DP3VIEWB10.0060
DP3WDOUT[0]11.3368
DP3WDOUT[1]11.3368
DP3WPSW[0]11.0066
DP3WPSW[1]11.0066
DP3ZIN0[0]32.67196
DP3ZIN0[1]32.67196
DP3ZIN1[0]23.83143
DP3ZIN1[1]23.83143
DP3ZIN2[0]15.0090
DP3ZIN2[1]15.0090
IDATRAP[0]22.67136
DP31ATRAP[0]22.67136
IDATRAP[1]22.67136
DP31ATRAP[1]22.67136
DP31BRAOUT2[0]16.67100
DP31BRAOUT2[1]16.67100
IDBRA[0]25.21151.25
IDBRA[1]25.21151.25
IDINTDIS[0]10.0060
IDINTDIS[1]10.0060
IDSYNC[0]16.83101
IDSYNC[1]16.83101
ICCBRANCH[1]25.17151
ICCBRANCH[0]25.17151
IM0ADR[17]38.33230
IM0ADR[16]38.33230
IM0ADR[15]42.50255
IM0ADR[14]42.50255
IM0ADR[13]42.50255
IM0ADR[12]42.50255
IM0ADR[11]42.50255
IM0ADR[10]42.50255
IM0ADR[9]42.50255
IM0ADR[8]42.50255
IM0ADR[7]38.67232
IM0ADR[6]38.67232
IM0ADR[5]38.67232
IM0ADR[4]38.67232
IM0ADR[3]38.67232
IM0ADR[2]38.67232
IM0ADR[1]38.67232
IM0ADR[0]38.67232
IM0WRITE[1]46.33278
IM0WRITE[0]46.33278
IM0WIDE[1]40.67244
IM0WIDE[0]40.67244
IM0RECEIVE[1]41.33248
IM0RECEIVE[0]41.33248
IM0HOLD[1]41.17247
IM0HOLD[0]41.17247
IM0DIWR[1]40.67244
IM0DIWR[0]40.67244
IM1ADR[17]26.67160
IM1ADR[16]26.67160
IM1ADR[15]26.67160
IM1ADR[14]26.67160
IM1ADR[13]26.67160
IM1ADR[12]26.67160
IM1ADR[11]26.67160
IM1ADR[10]26.67160
IM1ADR[9]26.67160
IM1ADR[8]26.67160
IM1ADR[7]26.00156
IM1ADR[6]26.00156
IM1ADR[5]26.00156
IM1ADR[4]26.00156
IM1ADR[3]26.00156
IM1ADR[2]26.00156
IM1ADR[1]26.00156
IM1ADR[0]26.00156
IM1WRITE[1]40.00240
IM1WRITE[0]40.00240
IM1WIDE[1]24.67148
IM1WIDE[0]24.67148
IM1RECEIVE[1]24.33146
IM1RECEIVE[0]24.33146
IM1HOLD[1]24.67148
IM1HOLD[0]24.67148
IM1DIWR[1]26.50159
IM1DIWR[0]26.50159
IM2ADR[17]13.0078
IM2ADR[16]13.0078
IM2ADR[15]18.33110
IM2ADR[14]18.33110
IM2ADR[13]19.00114
IM2ADR[12]19.00114
IM2ADR[11]20.00120
IM2ADR[10]20.00120
IM2ADR[9]20.17121
IM2ADR[8]20.17121
IM2ADR[7]20.00120
IM2ADR[6]20.00120
IM2ADR[5]19.00114
IM2ADR[4]19.00114
IM2ADR[3]18.33110
IM2ADR[2]18.33110
IM2ADR[1]18.00108
IM2ADR[0]18.00108
IM2WRITE[1]28.33170
IM2WRITE[0]28.33170
IM2WIDE[1]21.33128
IM2WIDE[0]21.33128
IM2RECEIVE[1]22.67136
IM2RECEIVE[0]22.67136
IM2HOLD[1]22.00132
IM2HOLD[0]22.00132
IM2DIWR[1]20.83125
IM2DIWR[0]20.83125
IM3ADR[17]8.0048
IM3ADR[16]8.0048
IM3ADR[15]9.1755
IM3ADR[14]9.1755
IM3ADR[13]9.1755
IM3ADR[12]9.1755
IM3ADR[11]9.1755
IM3ADR[10]9.1755
IM3ADR[9]10.5063
IM3ADR[8]10.5063
IM3ADR[7]10.0060
IM3ADR[6]10.0060
IM3ADR[5]9.6758
IM3ADR[4]9.6758
IM3ADR[3]9.0054
IM3ADR[2]9.0054
IM3ADR[1]9.0054
IM3ADR[0]9.0054
IM3WRITE[1]19.17115
IM3WRITE[0]19.17115
IM3WIDE[1]11.6770
IM3WIDE[0]11.6770
IM3RECEIVE[1]13.0078
IM3RECEIVE[0]13.0078
IM3HOLD[1]12.3374
IM3HOLD[0]12.3374
IM3DIWR[1]11.1767
IM3DIWR[0]11.1767
IM4ADR[17]25.00150
IM4ADR[16]25.00150
IM4ADR[15]26.00156
IM4ADR[14]26.00156
IM4ADR[13]26.67160
IM4ADR[12]26.67160
IM4ADR[11]27.33164
IM4ADR[10]27.33164
IM4ADR[9]27.83167
IM4ADR[8]27.83167
IM4ADR[7]27.33164
IM4ADR[6]27.33164
IM4ADR[5]26.67160
IM4ADR[4]26.67160
IM4ADR[3]26.17157
IM4ADR[2]26.17157
IM4ADR[1]25.67154
IM4ADR[0]25.67154
IM4WRITE[1]36.67220
IM4WRITE[0]36.67220
IM4WIDE[1]29.17175
IM4WIDE[0]29.17175
IM4RECEIVE[1]30.33182
IM4RECEIVE[0]30.33182
IM4HOLD[1]29.67178
IM4HOLD[0]29.67178
IM4DIWR[1]28.67172
IM4DIWR[0]28.67172
IM5ADR[17]35.83215
IM5ADR[16]35.83215
IM5ADR[15]35.67214
IM5ADR[14]35.67214
IM5ADR[13]35.17211
IM5ADR[12]35.17211
IM5ADR[11]34.83209
IM5ADR[10]34.83209
IM5ADR[9]34.67208
IM5ADR[8]34.67208
IM5ADR[7]36.00216
IM5ADR[6]36.00216
IM5ADR[5]35.67214
IM5ADR[4]35.67214
IM5ADR[3]35.33212
IM5ADR[2]35.33212
IM5ADR[1]35.00210
IM5ADR[0]35.00210
IM5WRITE[1]48.33290
IM5WRITE[0]48.33290
IM5WIDE[1]35.83215
IM5WIDE[0]35.83215
IM5RECEIVE[1]36.33218
IM5RECEIVE[0]36.33218
IM5HOLD[1]36.00216
IM5HOLD[0]36.00216
IM5DIWR[1]37.50225
IM5DIWR[0]37.50225
IM6ADR[17]46.50279
IM6ADR[16]46.50279
IM6ADR[15]47.83287
IM6ADR[14]47.83287
IM6ADR[13]48.67292
IM6ADR[12]48.67292
IM6ADR[11]49.67298
IM6ADR[10]49.67298
IM6ADR[9]50.50303
IM6ADR[8]50.50303
IM6ADR[7]47.67286
IM6ADR[6]47.67286
IM6ADR[5]47.33284
IM6ADR[4]47.33284
IM6ADR[3]47.00282
IM6ADR[2]47.00282
IM6ADR[1]46.67280
IM6ADR[0]46.67280
IM6WRITE[1]40.00240
IM6WRITE[0]40.00240
IM6WIDE[1]48.67292
IM6WIDE[0]48.67292
IM6RECEIVE[1]49.17295
IM6RECEIVE[0]49.17295
IM6HOLD[1]49.00294
IM6HOLD[0]49.00294
IM6DIWR[1]48.33290
IM6DIWR[0]48.33290
IM7ADR[17]43.83263
IM7ADR[16]43.83263
IM7ADR[15]43.50261
IM7ADR[14]43.50261
IM7ADR[13]43.33260
IM7ADR[12]43.33260
IM7ADR[11]42.83257
IM7ADR[10]42.83257
IM7ADR[9]42.67256
IM7ADR[8]42.67256
IM7ADR[7]44.00264
IM7ADR[6]44.00264
IM7ADR[5]43.83263
IM7ADR[4]43.83263
IM7ADR[3]43.33260
IM7ADR[2]43.33260
IM7ADR[1]43.17259
IM7ADR[0]43.17259
IM7WRITE[1]54.67328
IM7WRITE[0]54.67328
IM7WIDE[1]43.50261
IM7WIDE[0]43.50261
IM7RECEIVE[1]44.50267
IM7RECEIVE[0]44.50267
IM7HOLD[1]44.00264
IM7HOLD[0]44.00264
IM7DIWR[1]45.17271
IM7DIWR[0]45.17271
DM0ADR[17]16.1797
DM0ADR[16]16.1797
DM0ADR[15]16.0096
DM0ADR[14]16.0096
DM0ADR[13]16.0096
DM0ADR[12]16.0096
DM0ADR[11]16.0096
DM0ADR[10]16.0096
DM0ADR[9]16.0096
DM0ADR[8]16.0096
DM0ADR[7]15.8395
DM0ADR[6]15.8395
DM0ADR[5]15.8395
DM0ADR[4]15.8395
DM0ADR[3]15.8395
DM0ADR[2]15.8395
DM0ADR[1]15.8395
DM0ADR[0]15.8395
DM0WRITE[1]10.3362
DM0WRITE[0]10.3362
DM0WIDE[1]16.3398
DM0WIDE[0]16.3398
DM0RECEIVE[1]16.3398
DM0RECEIVE[0]16.3398
DM0HOLD[1]16.3398
DM0HOLD[0]16.3398
DM0DIWR[1]16.1797
DM0DIWR[0]16.1797
DM1ADR[17]22.33134
DM1ADR[16]22.33134
DM1ADR[15]22.33134
DM1ADR[14]22.33134
DM1ADR[13]22.33134
DM1ADR[12]22.33134
DM1ADR[11]22.33134
DM1ADR[10]22.33134
DM1ADR[9]22.83137
DM1ADR[8]22.83137
DM1ADR[7]22.83137
DM1ADR[6]22.83137
DM1ADR[5]22.83137
DM1ADR[4]22.83137
DM1ADR[3]22.83137
DM1ADR[2]22.83137
DM1ADR[1]22.83137
DM1ADR[0]22.83137
DM1WRITE[1]36.00216
DM1WRITE[0]36.00216
DM1WIDE[1]27.17163
DM1WIDE[0]27.17163
DM1RECEIVE[1]27.67166
DM1RECEIVE[0]27.67166
DM1HOLD[1]27.33164
DM1HOLD[0]27.33164
DM1DIWR[1]23.17139
DM1DIWR[0]23.17139
DM2ADR[17]25.67154
DM2ADR[16]25.67154
DM2ADR[15]25.50153
DM2ADR[14]25.50153
DM2ADR[13]25.50153
DM2ADR[12]25.50153
DM2ADR[11]25.50153
DM2ADR[10]25.50153
DM2ADR[9]25.50153
DM2ADR[8]25.50153
DM2ADR[7]25.50153
DM2ADR[6]25.50153
DM2ADR[5]25.50153
DM2ADR[4]25.50153
DM2ADR[3]25.50153
DM2ADR[2]25.50153
DM2ADR[1]25.50153
DM2ADR[0]25.50153
DM2WRITE[1]25.83155
DM2WRITE[0]25.83155
DM2WIDE[1]26.00156
DM2WIDE[0]26.00156
DM2RECEIVE[1]25.83155
DM2RECEIVE[0]25.83155
DM2HOLD[1]25.83155
DM2HOLD[0]25.83155
DM2DIWR[1]25.83155
DM2DIWR[0]25.83155
DM3ADR[17]37.67226
DM3ADR[16]37.67226
DM3ADR[15]37.67226
DM3ADR[14]37.67226
DM3ADR[13]38.00228
DM3ADR[12]38.00228
DM3ADR[11]38.33230
DM3ADR[10]38.33230
DM3ADR[9]38.50231
DM3ADR[8]38.50231
DM3ADR[7]36.50219
DM3ADR[6]36.50219
DM3ADR[5]37.33224
DM3ADR[4]37.33224
DM3ADR[3]37.83227
DM3ADR[2]37.83227
DM3ADR[1]37.50225
DM3ADR[0]37.50225
DM3WRITE[1]32.50195
DM3WRITE[0]32.50195
DM3WIDE[1]40.50243
DM3WIDE[0]40.50243
DM3RECEIVE[1]40.33242
DM3RECEIVE[0]40.33242
DM3HOLD[1]40.50243
DM3HOLD[0]40.50243
DM3DIWR[1]37.00222
DM3DIWR[0]37.00222
DM4ADR[17]24.50147
DM4ADR[16]24.50147
DM4ADR[15]33.33200
DM4ADR[14]33.33200
DM4ADR[13]33.33200
DM4ADR[12]33.33200
DM4ADR[11]33.33200
DM4ADR[10]33.33200
DM4ADR[9]33.33200
DM4ADR[8]33.33200
DM4ADR[7]33.33200
DM4ADR[6]33.33200
DM4ADR[5]33.33200
DM4ADR[4]33.33200
DM4ADR[3]33.33200
DM4ADR[2]33.33200
DM4ADR[1]33.33200
DM4ADR[0]33.33200
DM4WRITE[1]28.33170
DM4WRITE[0]28.33170
DM4WIDE[1]33.67202
DM4WIDE[0]33.67202
DM4RECEIVE[1]33.67202
DM4RECEIVE[0]33.67202
DM4HOLD[1]33.67202
DM4HOLD[0]33.67202
DM4DIWR[1]33.67202
DM4DIWR[0]33.67202
DM5ADR[17]48.33290
DM5ADR[16]48.33290
DM5ADR[15]48.67292
DM5ADR[14]48.67292
DM5ADR[13]49.50297
DM5ADR[12]49.50297
DM5ADR[11]50.00300
DM5ADR[10]50.00300
DM5ADR[9]51.17307
DM5ADR[8]51.17307
DM5ADR[7]45.83275
DM5ADR[6]45.83275
DM5ADR[5]46.67280
DM5ADR[4]46.67280
DM5ADR[3]47.50285
DM5ADR[2]47.50285
DM5ADR[1]47.50285
DM5ADR[0]47.50285
DM5WRITE[1]39.33236
DM5WRITE[0]39.33236
DM5WIDE[1]47.17283
DM5WIDE[0]47.17283
DM5RECEIVE[1]46.50279
DM5RECEIVE[0]46.50279
DM5HOLD[1]46.83281
DM5HOLD[0]46.83281
DM5DIWR[1]43.67262
DM5DIWR[0]43.67262
DM6ADR[17]46.67280
DM6ADR[16]46.67280
DM6ADR[15]46.00276
DM6ADR[14]46.00276
DM6ADR[13]45.83275
DM6ADR[12]45.83275
DM6ADR[11]45.50273
DM6ADR[10]45.50273
DM6ADR[9]45.00270
DM6ADR[8]45.00270
DM6ADR[7]47.33284
DM6ADR[6]47.33284
DM6ADR[5]47.00282
DM6ADR[4]47.00282
DM6ADR[3]46.67280
DM6ADR[2]46.67280
DM6ADR[1]46.33278
DM6ADR[0]46.33278
DM6WRITE[1]39.83239
DM6WRITE[0]39.83239
DM6WIDE[1]47.83287
DM6WIDE[0]47.83287
DM6RECEIVE[1]48.50291
DM6RECEIVE[0]48.50291
DM6HOLD[1]48.17289
DM6HOLD[0]48.17289
DM6DIWR[1]47.50285
DM6DIWR[0]47.50285
DM7ADR[17]53.33320
DM7ADR[16]53.33320
DM7ADR[15]53.83323
DM7ADR[14]53.83323
DM7ADR[13]54.67328
DM7ADR[12]54.67328
DM7ADR[11]54.67328
DM7ADR[10]54.67328
DM7ADR[9]55.00330
DM7ADR[8]55.00330
DM7ADR[7]51.83311
DM7ADR[6]51.83311
DM7ADR[5]52.50315
DM7ADR[4]52.50315
DM7ADR[3]53.50321
DM7ADR[2]53.50321
DM7ADR[1]53.33320
DM7ADR[0]53.33320
DM7WRITE[1]48.83293
DM7WRITE[0]48.83293
DM7WIDE[1]54.50327
DM7WIDE[0]54.50327
DM7RECEIVE[1]54.50327
DM7RECEIVE[0]54.50327
DM7HOLD[1]55.00330
DM7HOLD[0]55.00330
DM7DIWR[1]51.33308
DM7DIWR[0]51.33308

APPENDIX H

Mentor Database Information

1. Mentor system can be started by typing "dmgr" at the unix command prompt.

2. This brings up a tool manager from which you can launch any CAD tool. The available tools are displayed in the left tool window.

3. Mentor database is always is stored in a directory "mgc" in the user's home directory. The backup copies are named mgcbak0/mgcbak1/mgcbak2/... and so on.

4. There is an extra copy of databse with the asumption of deskew chip. It is called mgc-deskew-aug17. To use this copy change the directory name to mgc (first moving the original mgc somewhere) and run dmgr.

5. The friscg files are in mgc -> projects -> mcm -> friscg directory.

6. The design name is friscg.

7. The pcb subdirectory inside the friscg directory contains all the netlists, and artwork for the MCM.

8. All the manuals are on the window ledge in the SUN room. An online copy of the manuals is available on a CDROM which is in the file cabinet.

9. Two tutorial manuals (one book and one exercise book) for board design are also in the SUN room. They are simple enough and can bring up anybody up to speed in a short time.

APPENDIX I

QSIM INPUT FOR CACHE RAM SIMULATION

***********************************************************************

Filename : /bigtmp/cache_norm_q.sim

***********************************************************************

vector doh[3:0] d3out.ltchPAD.PAD1 d2out.ltchPAD.PAD1 d1out.ltchPAD.PAD1 d0out.ltchpad.PAD1

vector dol[3:0] d3out.ltchPAD.PAD0 d2out.ltchPAD.PAD0 d1out.ltchPAD.PAD0 d0out.ltchpad.PAD0

vector dih[3:0] Din3Pad.dlmxpad.PAD1 Din2Pad.dlmxpad.PAD1 Din1Pad.dlmxpad.PAD1 Din0Pad.dlmxpad.PAD1

vector dil[3:0] Din3Pad.dlmxpad.PAD0 Din2Pad.dlmxpad.PAD0 Din1Pad.dlmxpad.PAD0 Din0Pad.dlmxpad.PAD0

vector ah[4:0] A8pad.dlmxpad.PAD1 A7pad.dlmxpad.PAD1 A6pad.dlmxpad.PAD1 A5pad.dlmxpad.PAD1 A4pad.dlmxpad.PAD1

vector al[4:0] A8pad.dlmxpad.PAD0 A7pad.dlmxpad.PAD0 A6pad.dlmxpad.PAD0 A5pad.dlmxpad.PAD0 A4pad.dlmxpad.PAD0

vector nh[3:0] A3pad.dlmxpad.PAD1 A2pad.dlmxpad.PAD1 A1pad.dlmxpad.PAD1 A0pad.dlmxpad.PAD1

vector nl[3:0] A3pad.dlmxpad.PAD0 A2pad.dlmxpad.PAD0 A1pad.dlmxpad.PAD0 A0pad.dlmxpad.PAD0

vector dointh[3:0] do[7] do[5] do[3] do[1]

vector dointl[3:0] do[6] do[4] do[2] do[0]

vector diinth[3:0] dint[7] dint[5] dint[3] dint[1]

vector diintl[3:0] dint[6] dint[4] dint[2] dint[0]

vector b0dib[3:0] b0di[7] b0di[5] b0di[3] b0di[1]

vector b1dib[3:0] b1di[7] b1di[5] b1di[3] b1di[1]

vector b2dib[3:0] b2di[7] b2di[5] b2di[3] b2di[1]

vector b3dib[3:0] b3di[7] b3di[5] b3di[3] b3di[1]

vector b0nib0[3:0] topblk.twoblks.rfmo_cr_xtr.DO3[1] topblk.twoblks.rfmo_cr_xtr.DO2[1] topblk.twoblks.rfmo_cr_xtr.DO1[1] topblk.twoblks.rfmo_cr_xtr.DO0[1]

vector b3nib3[3:0] btmblk.twoblks.rfmo_cr_xtr.DO15[1] btmblk.twoblks.rfmo_cr_xtr.DO14[1] btmblk.twoblks.rfmo_cr_xtr.DO13[1] btmblk.twoblks.rfmo_cr_xtr.DO12[1]

vector b0blkout[15:0] topblk.twoblks.rfmo_cr_xtr.DO15[1] -

topblk.twoblks.rfmo_cr_xtr.DO14[1] topblk.twoblks.rfmo_cr_xtr.DO13[1] -

topblk.twoblks.rfmo_cr_xtr.DO12[1] topblk.twoblks.rfmo_cr_xtr.DO11[1] -

topblk.twoblks.rfmo_cr_xtr.DO10[1] topblk.twoblks.rfmo_cr_xtr.DO9[1] -

topblk.twoblks.rfmo_cr_xtr.DO8[1] topblk.twoblks.rfmo_cr_xtr.DO7[1] -

topblk.twoblks.rfmo_cr_xtr.DO6[1] topblk.twoblks.rfmo_cr_xtr.DO5[1] -

topblk.twoblks.rfmo_cr_xtr.DO4[1] topblk.twoblks.rfmo_cr_xtr.DO3[1] -

topblk.twoblks.rfmo_cr_xtr.DO2[1] topblk.twoblks.rfmo_cr_xtr.DO1[1] -

topblk.twoblks.rfmo_cr_xtr.DO0[1]

vector b1blkout[15:0] topblk.twoblks.rfmo_cr_xtr$1.DO15[1] -

topblk.twoblks.rfmo_cr_xtr$1.DO14[1] topblk.twoblks.rfmo_cr_xtr$1.DO13[1] -

topblk.twoblks.rfmo_cr_xtr$1.DO12[1] topblk.twoblks.rfmo_cr_xtr$1.DO11[1] -

topblk.twoblks.rfmo_cr_xtr$1.DO10[1] topblk.twoblks.rfmo_cr_xtr$1.DO9[1] -

topblk.twoblks.rfmo_cr_xtr$1.DO8[1] topblk.twoblks.rfmo_cr_xtr$1.DO7[1] -

topblk.twoblks.rfmo_cr_xtr$1.DO6[1] topblk.twoblks.rfmo_cr_xtr$1.DO5[1] -

topblk.twoblks.rfmo_cr_xtr$1.DO4[1] topblk.twoblks.rfmo_cr_xtr$1.DO3[1] -

topblk.twoblks.rfmo_cr_xtr$1.DO2[1] topblk.twoblks.rfmo_cr_xtr$1.DO1[1] -

topblk.twoblks.rfmo_cr_xtr$1.DO0[1]

vector b3blkout[15:0] btmblk.twoblks.rfmo_cr_xtr.DO15[1] -

btmblk.twoblks.rfmo_cr_xtr.DO14[1] btmblk.twoblks.rfmo_cr_xtr.DO13[1] -

btmblk.twoblks.rfmo_cr_xtr.DO12[1] btmblk.twoblks.rfmo_cr_xtr.DO11[1] -

btmblk.twoblks.rfmo_cr_xtr.DO10[1] btmblk.twoblks.rfmo_cr_xtr.DO9[1] -

btmblk.twoblks.rfmo_cr_xtr.DO8[1] btmblk.twoblks.rfmo_cr_xtr.DO7[1] -

btmblk.twoblks.rfmo_cr_xtr.DO6[1] btmblk.twoblks.rfmo_cr_xtr.DO5[1] -

btmblk.twoblks.rfmo_cr_xtr.DO4[1] btmblk.twoblks.rfmo_cr_xtr.DO3[1] -

btmblk.twoblks.rfmo_cr_xtr.DO2[1] btmblk.twoblks.rfmo_cr_xtr.DO1[1] -

btmblk.twoblks.rfmo_cr_xtr.DO0[1]

vector b2blkout[15:0] btmblk.twoblks.rfmo_cr_xtr$1.DO15[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DO14[1] btmblk.twoblks.rfmo_cr_xtr$1.DO13[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DO12[1] btmblk.twoblks.rfmo_cr_xtr$1.DO11[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DO10[1] btmblk.twoblks.rfmo_cr_xtr$1.DO9[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DO8[1] btmblk.twoblks.rfmo_cr_xtr$1.DO7[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DO6[1] btmblk.twoblks.rfmo_cr_xtr$1.DO5[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DO4[1] btmblk.twoblks.rfmo_cr_xtr$1.DO3[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DO2[1] btmblk.twoblks.rfmo_cr_xtr$1.DO1[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DO0[1]

vector b0blkin[15:0] topblk.twoblks.rfmo_cr_xtr.DI15[1] -

topblk.twoblks.rfmo_cr_xtr.DI14[1] topblk.twoblks.rfmo_cr_xtr.DI13[1] -

topblk.twoblks.rfmo_cr_xtr.DI12[1] topblk.twoblks.rfmo_cr_xtr.DI11[1] -

topblk.twoblks.rfmo_cr_xtr.DI10[1] topblk.twoblks.rfmo_cr_xtr.DI9[1] -

topblk.twoblks.rfmo_cr_xtr.DI8[1] topblk.twoblks.rfmo_cr_xtr.DI7[1] -

topblk.twoblks.rfmo_cr_xtr.DI6[1] topblk.twoblks.rfmo_cr_xtr.DI5[1] -

topblk.twoblks.rfmo_cr_xtr.DI4[1] topblk.twoblks.rfmo_cr_xtr.DI3[1] -

topblk.twoblks.rfmo_cr_xtr.DI2[1] topblk.twoblks.rfmo_cr_xtr.DI1[1] -

topblk.twoblks.rfmo_cr_xtr.DI0[1]

vector b1blkin[15:0] topblk.twoblks.rfmo_cr_xtr$1.DI15[1] -

topblk.twoblks.rfmo_cr_xtr$1.DI14[1] topblk.twoblks.rfmo_cr_xtr$1.DI13[1] -

topblk.twoblks.rfmo_cr_xtr$1.DI12[1] topblk.twoblks.rfmo_cr_xtr$1.DI11[1] -

topblk.twoblks.rfmo_cr_xtr$1.DI10[1] topblk.twoblks.rfmo_cr_xtr$1.DI9[1] -

topblk.twoblks.rfmo_cr_xtr$1.DI8[1] topblk.twoblks.rfmo_cr_xtr$1.DI7[1] -

topblk.twoblks.rfmo_cr_xtr$1.DI6[1] topblk.twoblks.rfmo_cr_xtr$1.DI5[1] -

topblk.twoblks.rfmo_cr_xtr$1.DI4[1] topblk.twoblks.rfmo_cr_xtr$1.DI3[1] -

topblk.twoblks.rfmo_cr_xtr$1.DI2[1] topblk.twoblks.rfmo_cr_xtr$1.DI1[1] -

topblk.twoblks.rfmo_cr_xtr$1.DI0[1]

vector b3blkin[15:0] btmblk.twoblks.rfmo_cr_xtr.DI15[1] -

btmblk.twoblks.rfmo_cr_xtr.DI14[1] btmblk.twoblks.rfmo_cr_xtr.DI13[1] -

btmblk.twoblks.rfmo_cr_xtr.DI12[1] btmblk.twoblks.rfmo_cr_xtr.DI11[1] -

btmblk.twoblks.rfmo_cr_xtr.DI10[1] btmblk.twoblks.rfmo_cr_xtr.DI9[1] -

btmblk.twoblks.rfmo_cr_xtr.DI8[1] btmblk.twoblks.rfmo_cr_xtr.DI7[1] -

btmblk.twoblks.rfmo_cr_xtr.DI6[1] btmblk.twoblks.rfmo_cr_xtr.DI5[1] -

btmblk.twoblks.rfmo_cr_xtr.DI4[1] btmblk.twoblks.rfmo_cr_xtr.DI3[1] -

btmblk.twoblks.rfmo_cr_xtr.DI2[1] btmblk.twoblks.rfmo_cr_xtr.DI1[1] -

btmblk.twoblks.rfmo_cr_xtr.DI0[1]

vector b2blkin[15:0] btmblk.twoblks.rfmo_cr_xtr$1.DI15[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DI14[1] btmblk.twoblks.rfmo_cr_xtr$1.DI13[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DI12[1] btmblk.twoblks.rfmo_cr_xtr$1.DI11[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DI10[1] btmblk.twoblks.rfmo_cr_xtr$1.DI9[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DI8[1] btmblk.twoblks.rfmo_cr_xtr$1.DI7[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DI6[1] btmblk.twoblks.rfmo_cr_xtr$1.DI5[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DI4[1] btmblk.twoblks.rfmo_cr_xtr$1.DI3[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DI2[1] btmblk.twoblks.rfmo_cr_xtr$1.DI1[1] -

btmblk.twoblks.rfmo_cr_xtr$1.DI0[1]

vector b3nib3[3:0] btmblk.twoblks.rfmo_cr_xtr.DO15[1] btmblk.twoblks.rfmo_cr_xtr.DO14[1] btmblk.twoblks.rfmo_cr_xtr.DO13[1] btmblk.twoblks.rfmo_cr_xtr.DO12[1]

set external bidirectional b0pad$15.bipad.PAD1 b0pad$14.bipad.PAD1 b0pad$13.bipad.PAD1 b0pad$12.bipad.PAD1 b0pad$11.bipad.PAD1 b0pad$10.bipad.PAD1 b0pad$9.bipad.PAD1 b0pad$8.bipad.PAD1 b0pad$7.bipad.PAD1 b0pad$6.bipad.PAD1 b0pad$5.bipad.PAD1 b0pad$4.bipad.PAD1 b0pad$3.bipad.PAD1 b0pad$2.bipad.PAD1 b0pad$1.bipad.PAD1 b0pad$0.bipad.PAD1

set external bidirectional b0pad$15.bipad.PAD0 b0pad$14.bipad.PAD0 b0pad$13.bipad.PAD0 b0pad$12.bipad.PAD0 b0pad$11.bipad.PAD0 b0pad$10.bipad.PAD0 b0pad$9.bipad.PAD0 b0pad$8.bipad.PAD0 b0pad$7.bipad.PAD0 b0pad$6.bipad.PAD0 b0pad$5.bipad.PAD0 b0pad$4.bipad.PAD0 b0pad$3.bipad.PAD0 b0pad$2.bipad.PAD0 b0pad$1.bipad.PAD0 b0pad$0.bipad.PAD0

vector b0dwdh[15:0] b0pad$15.bipad.PAD1 b0pad$14.bipad.PAD1 b0pad$13.bipad.PAD1 b0pad$12.bipad.PAD1 b0pad$11.bipad.PAD1 b0pad$10.bipad.PAD1 b0pad$9.bipad.PAD1 b0pad$8.bipad.PAD1 b0pad$7.bipad.PAD1 b0pad$6.bipad.PAD1 b0pad$5.bipad.PAD1 b0pad$4.bipad.PAD1 b0pad$3.bipad.PAD1 b0pad$2.bipad.PAD1 b0pad$1.bipad.PAD1 b0pad$0.bipad.PAD1

vector b3nib3[3:0] btmblk.twoblks.rfmo_cr_xtr.DO15[1] btmblk.twoblks.rfmo_cr_xtr.DO14[1] btmblk.twoblks.rfmo_cr_xtr.DO13[1] btmblk.twoblks.rfmo_cr_xtr.DO12[1]

set external bidirectional b0pad$15.bipad.PAD1 b0pad$14.bipad.PAD1 b0pad$13.bipad.PAD1 b0pad$12.bipad.PAD1 b0pad$11.bipad.PAD1 b0pad$10.bipad.PAD1 b0pad$9.bipad.PAD1 b0pad$8.bipad.PAD1 b0pad$7.bipad.PAD1 b0pad$6.bipad.PAD1 b0pad$5.bipad.PAD1 b0pad$4.bipad.PAD1 b0pad$3.bipad.PAD1 b0pad$2.bipad.PAD1 b0pad$1.bipad.PAD1 b0pad$0.bipad.PAD1

set external bidirectional b0pad$15.bipad.PAD0 b0pad$14.bipad.PAD0 b0pad$13.bipad.PAD0 b0pad$12.bipad.PAD0 b0pad$11.bipad.PAD0 b0pad$10.bipad.PAD0 b0pad$9.bipad.PAD0 b0pad$8.bipad.PAD0 b0pad$7.bipad.PAD0 b0pad$6.bipad.PAD0 b0pad$5.bipad.PAD0 b0pad$4.bipad.PAD0 b0pad$3.bipad.PAD0 b0pad$2.bipad.PAD0 b0pad$1.bipad.PAD0 b0pad$0.bipad.PAD0

vector b0dwdh[15:0] b0pad$15.bipad.PAD1 b0pad$14.bipad.PAD1 b0pad$13.bipad.PAD1 b0pad$12.bipad.PAD1 b0pad$11.bipad.PAD1 b0pad$10.bipad.PAD1 b0pad$9.bipad.PAD1 b0pad$8.bipad.PAD1 b0pad$7.bipad.PAD1 b0pad$6.bipad.PAD1 b0pad$5.bipad.PAD1 b0pad$4.bipad.PAD1 b0pad$3.bipad.PAD1 b0pad$2.bipad.PAD1 b0pad$1.bipad.PAD1 b0pad$0.bipad.PAD1

vector b0dwdl[15:0] b0pad$15.bipad.PAD0 b0pad$14.bipad.PAD0 b0pad$13.bipad.PAD0 b0pad$12.bipad.PAD0 b0pad$11.bipad.PAD0 b0pad$10.bipad.PAD0 b0pad$9.bipad.PAD0 b0pad$8.bipad.PAD0 b0pad$7.bipad.PAD0 b0pad$6.bipad.PAD0 b0pad$5.bipad.PAD0 b0pad$4.bipad.PAD0 b0pad$3.bipad.PAD0 b0pad$2.bipad.PAD0 b0pad$1.bipad.PAD0 b0pad$0.bipad.PAD0

vector b0dinib[3:0] b0di[7] b0di[5] b0di[3] b0di[1]

vector blkadrint[4:0] ADDR_INT[17] ADDR_INT[15] ADDR_INT[13] ADDR_INT[11] ADDR_INT[9]

vector seladrint[3:0] ADDR_INT[7] ADDR_INT[5] ADDR_INT[3] ADDR_INT[1]

vector atopb[4:0] ATOP[9] ATOP[7] ATOP[5] ATOP[3] ATOP[1]

vector abtmb[4:0] ABTM[9] ABTM[7] ABTM[5] ABTM[3] ABTM[1]

vector b0donib[3:0] b0do[7] b0do[5] b0do[3] b0do[1]

vector b1donib[3:0] b1do[7] b1do[5] b1do[3] b1do[1]

vector b2donib[3:0] b2do[7] b2do[5] b2do[3] b2do[1]

vector b3donib[3:0] b3do[7] b3do[5] b3do[3] b3do[1]

vector nibtopb[3:0] NIBTOP[7] NIBTOP[5] NIBTOP[3] NIBTOP[1]

vector nibbtmb[3:0] NIBBTM[7] NIBBTM[5] NIBBTM[3] NIBBTM[1]

vector blkwrb[3:0] BLKWR[7] BLKWR[5] BLKWR[3] BLKWR[1]

vector driveb[3:0] drive[7] drive[5] drive[3] drive[1]

vector nibselb[1:0] topblk.NIBSEL1[1] topblk.NIBSEL0[1]

vector dxout[3:0] d3out.ltchPAD.q[1] d2out.ltchPAD.q[1] d1out.ltchPAD.q[1] d0out.ltchPAD.q[1]

vector dpselb[3:0] DPSEL[7] DPSEL[5] DPSEL[3] DPSEL[1]

set radix 16 b3blkout b2blkout b1blkout b0blkout b0dwdh

set radix 16 b3blkin b2blkin b1blkin b0blkin

set radix 16 b3donib b2donib b1donib b0donib

set radix 16 nibtopb nibbtmb blkwrb

watch (always) doh dxout dointh dih

#watch (always) b3dib b2dib b1dib b0dib

watch (always) b3blkin b2blkin b1blkin b0blkin

watch (always) ah nh

watch (always) b0dinib blkadrint seladrint blkdec.A[5]

watch (always) atopb abtmb nibselb

watch (always) b3blkout b2blkout b1blkout b0blkout

watch (always) b3donib b2donib b1donib b0donib

watch (always) write.mxcpad.PAD1 write_int[1] wrcore[1]

watch (always) blkwrb

watch (always) nibtopb nibbtmb

watch (always) hold_int[1] pp_data[1] INP_SEL[1] HLDLTOUT[1]

watch (always) wide.dlmxpad.PAD1 wide_int[1] dpselb

watch (always) driveb

#watch (always) b0dwdh

#echo zero topblk.twoblks.blk0.rfmo

#request topblk.twoblks.rfmo_cr_xtr zero

#echo zero topblk.twoblks.blk1.rfmo

#request topblk.twoblks.rfmo_cr_xtr$1 zero

#echo zero btmblk.twoblks.blk0.rfmo

#request btmblk.twoblks.rfmo_cr_xtr zero

#echo zero btmblk.twoblks.blk1.rfmo

#request btmblk.twoblks.rfmo_cr_xtr$1 zero

l SCAN.U5.PAD

h scan_clk[1]

l scan_clk[0]

l RECEIVE.dlmxpad.PAD1

h RECEIVE.dlmxpad.PAD0

h TEST.serpu.PAD

l wide.dlmxpad.PAD1

h wide.dlmxpad.PAD0

l HOLD.mxopad.PAD1

h HOLD.mxopad.PAD0

l write.mxcpad.PAD1

h write.mxcpad.PAD0

l hsclk.U5.PAD

h DIWR.dlmxpad.PAD1

l DIWR.dlmxpad.PAD0

step 1000

h hsclk.PAD

step 1000

l hsclk.PAD

step 1000

h hsclk.PAD

step 1000

l hsclk.PAD

step 1000

sv dih 'b1111

sv dil 'b0000

sv ah 'b00000

sv al 'b11111

sv nh 'b0000

sv nl 'b1111

step 10000

h write.mxcpad.PAD1

l write.mxcpad.PAD0

step 10000

l write.mxcpad.PAD1

h write.mxcpad.PAD0

step 10000

sv dih 'b0000

sv dil 'b1111

sv ah 'b11111

sv al 'b00000

sv nh 'b1111

sv nl 'b0000

step 10000

h write.mxcpad.PAD1

l write.mxcpad.PAD0

step 10000

l write.mxcpad.PAD1

h write.mxcpad.PAD0

step 10000

sv dih 'b1111

sv dil 'b0000

sv ah 'b00000

sv al 'b11111

sv nh 'b0101

sv nl 'b1010

step 10000

h write.mxcpad.PAD1

l write.mxcpad.PAD0

step 10000

l write.mxcpad.PAD1

h write.mxcpad.PAD0

step 10000

sv dih 'b0000

sv dil 'b1111

sv ah 'b11111

sv al 'b00000

sv nh 'b1010

sv nl 'b0101

step 10000

h write.mxcpad.PAD1

l write.mxcpad.PAD0

step 10000

l write.mxcpad.PAD1

h write.mxcpad.PAD0

step 10000

echo DUMP blk0

request topblk.twoblks.rfmo_cr_xtr dump

echo DUMP blk1

request topblk.twoblks.rfmo_cr_xtr$1 dump

echo DUMP blk2

request btmblk.twoblks.rfmo_cr_xtr$1 dump

echo DUMP blk3

request btmblk.twoblks.rfmo_cr_xtr dump

sv ah 'b00000

sv al 'b11111

sv nh 'b0000

sv nl 'b1111

step 10000

sv ah 'b11111

sv al 'b00000

sv nh 'b1111

sv nl 'b0000

step 10000

sv ah 'b00000

sv al 'b11111

sv nh 'b0101

sv nl 'b1010

step 10000

sv ah 'b11111

sv al 'b00000

sv nh 'b1010

sv nl 'b0101

step 10000

h RECEIVE.dlmxpad.PAD1

l RECEIVE.dlmxpad.PAD0

h wide.dlmxpad.PAD1

l wide.dlmxpad.PAD0

sv al 'b00000

sv ah 'b11111

sv nl 'b1100

sv nh 'b0011

step 1000

sv b0dwdh 'hAAAA

sv b0dwdl 'h5555

h write.mxcpad.PAD1

l write.mxcpad.PAD0

step 2000

l write.mxcpad.PAD1

h write.mxcpad.PAD0

step 500

echo DUMP blk0

request topblk.twoblks.rfmo_cr_xtr dump

echo DUMP blk1

request topblk.twoblks.rfmo_cr_xtr$1 dump

echo DUMP blk2

request btmblk.twoblks.rfmo_cr_xtr$1 dump

echo DUMP blk3

request btmblk.twoblks.rfmo_cr_xtr dump

l RECEIVE.dlmxpad.PAD1

h RECEIVE.dlmxpad.PAD0

step 500

set charged * b0pad$15.bipad.PAD1 b0pad$14.bipad.PAD1 b0pad$13.bipad.PAD1 b0pad$12.bipad.PAD1 b0pad$11.bipad.PAD1 b0pad$10.bipad.PAD1 b0pad$9.bipad.PAD1 b0pad$8.bipad.PAD1 b0pad$7.bipad.PAD1 b0pad$6.bipad.PAD1 b0pad$5.bipad.PAD1 b0pad$4.bipad.PAD1 b0pad$3.bipad.PAD1 b0pad$2.bipad.PAD1 b0pad$1.bipad.PAD1 b0pad$0.bipad.PAD1

set charged * b0pad$15.bipad.PAD0 b0pad$14.bipad.PAD0 b0pad$13.bipad.PAD0 b0pad$12.bipad.PAD0 b0pad$11.bipad.PAD0 b0pad$10.bipad.PAD0 b0pad$9.bipad.PAD0 b0pad$8.bipad.PAD0 b0pad$7.bipad.PAD0 b0pad$6.bipad.PAD0 b0pad$5.bipad.PAD0 b0pad$4.bipad.PAD0 b0pad$3.bipad.PAD0 b0pad$2.bipad.PAD0 b0pad$1.bipad.PAD0 b0pad$0.bipad.PAD0

step 1000

sv ah 'b00000

sv al 'b11111

sv nh 'b0000

sv nl 'b1111

step 1000

sv al 'b00000

sv ah 'b11111

sv nl 'b1100

sv nh 'b0011

step 1000

h HOLD.mxopad.PAD1

l HOLD.mxopad.PAD0

l DIWR.dlmxpad.PAD1

h DIWR.dlmxpad.PAD0

step 1000

QSIM OUTPUT

APPENDIX J

Process Summary File

Mentor Version - A 8.4_1 on SunOS4.1.3_U1

Database Info

~forman/mentor/rpi/friscg (dir) - contains the latest mentor database at GE.

~forman/mentor/rpi/frisc (dir) - contains the old mentor database at GE.

~garg/mgc - contains the latest database at RPI.

~garg/mgc-deskew - contains the latest database with deskew chip at RPI.

Top Level Design Name - friscg

master-GDS.CFG - master file for GDS to HDI layer mapping.

master-adi-defaults - master file for drc

mcm11 (dir) - contains files for MT0 + LEG

mcm2 (dir) - ...................MT1 + LEG

mcm3 (dir) - ...................MT2 + LEG

mcm4 (dir) - ...................MT3 + LEG

mcm5 (dir) - ...................MT4 + LEG

mcm6 (dir) - ...................MT5 + LEG

Layer Stack-up

------------------------------------------- MT6 (4.5 um)

------------------------------------------- MT5 (4.5 um)

------------------------------------------- MT4 (4.5 um)

------------------------------------------- MT3 (4.5 um)

------------------------------------------- MT2 (10 um)

------------------------------------------- MT1 (10 um)

------------------------------------------- MT0 (10 um for soldering I/O)

Neutral File

~forman/mentor/rpi/friscg/pcb/mfg/neutral_file

~garg/mgc/projects/mcm/friscg/pcb/mfg/neutral_file

Mechanical File

1. Raw Substrate Size - 110 mm x 110 mm x 2.5 mm

2. Sawn Substrate Size - Same

3. Thickness - 100 mils

4. Milled Fiducial Locations - Top Left and Lower Left

5. Laser Fiducial Locations - Top Left and Lower left

6. Component Count - 23

7. Die requiring backside contact - None

8. Beveled pockets - None

9. Non-standard corner relief pockets - See Figure 5-40 in thesis

10. Number of DHDI metal layers - 6

11. Layer sequence - MT0/MT1/MT2/MT3/MT4/MT5/MT6

12. Unbeveled pockets requiring MT0 coverage - None

Milling

1. Correct .MSR files for all components

~forman/mentor/rpi/measure-files/*.msr (* = id,dp,cc,cr)

~garg/mgc/projects/measure-files/*.msr (* = id,dp,cc,cr)

2. Any issues relative to .MSR file origin

and/or accuracy - After Die arrive

3. .PLS file complete

4. .CMP file

5. Raw Substrate Materials - AlN

6. Unusual process requirements at mill

Die Attach

1. Die attachment material - 84-1LMI + Silvar, or Loaded SDAN (loaded with Cabosil)

2. Bake out condition of the die attach material - Standard

3. Unusual die requirements - None

4. Any components placed at < 15 mils spacing - None

5. Any unusual process requirements at die attach - None

CAD

1. Design Files DRC'd - Yes

2. Specify design rule violations and their disposition

- Nominal - 36 um width, 39 um space

- In the pads areas - 25 um width, 32.5 um space to nearest pad

- IC Pad size - 75 um x 75 um

3. Design Files ERC'd - No

4. Specify any electrical rule violation and their disposition

- None

5. Design Files LVL'd - No

6. Specify any LVL inconsistencies and their disposition

- None

7. Are there double DR-1's to all ICs? - No

8. Has the M0 layer been designed to accommodate standard "die attach"

fiducials and/or component placement alignment marks?

- Yes

11. Has an ALM file been generated for this module?

- ALM layer contains all the location markers.

12. Have schematic representations of all "non-standard" DR1-ALM points been supplied to processing?

- NA

13. Specify any non-adaptive laser layers - None

14. Specify any further changes required to the existing files

- None

Processing

1. Do we have substrate carriers? - GE needs to make carriers

2. Do we need to order carriers? If yes who will order? - Glenn Forman

3. Are there any other unusual fixturing for the DHDI manufacturing sequence?

- No

Process Summary

1. Substrates

Material Type - sawed to dimension 110+-1 mm x 110+-1 mm x 100 mils

2. Carrier Material - Ti

Thickness - 100 mils

Backed - No

3. Milling

Internal

Offsets - centered

4. Metal-0

1000 A Ti/ 1000 A Cu/ 10 um plated Cu/ 1000 A Ti

Dry Etch Ti Layer

Pre-tinned the bare Cu

Will need pre-tinned Cu on flex

Use 60 Pb/40 Sn solder between MT0 and Flex

5. None

6. Die attach

MRSI

Use the material that demonstrates best glue line and pull strength with AlN

7. Lamination 1

STD 15 um UL10B on 25 um Kapton E (H - optional)

8. Upper Laminations

STD 13 um SPI-Epoxy / 25 um Kapton E (H - optional)

9. Via drilling

Single drills to ICs

10. Metal Thickness

MT6 (4.5 um) - Ti/Cu/Ti/TiW/Au

MT5 (4.5 um) - Ti/Cu/Ti

MT4 (4.5 um) - "

MT3 (4.5 um) - "

MT2 (10 um) - "

MT1 (10 um) - "

MT0 (10 um for soldering I/O) - see above

11. See above

12. None

13. Passivation - None

14. Ablation requirements - None

15. None

16. Testing after the first layer

Deliver to RPI for testing after Metal 1 is patterned

Other Information

Work to be done prior to FAB

1. Add MT0 mill fid cover metal

2. Add laser fiducial

- all layers

- anywhere around outer circuit border

3. Generate .MSR files from geoms - verify with die

4. Generate .CMP, .PLS, .MEC

5. Design review w/FAB + RPI

6. Order substrate material

7. Order Ti Carrier