The test chip was fabricated at Rockwell International during
the Fall of 1994 and both wafers and lapped reticles were received
at Rensselaer in December 1994. S-parameter measurements on all
the capacitors and devices were done at Rockwell. The ring oscillators
and the resistor structures were tested at Rensselaer. A few measurements
were also repeated outside Rensselaer to double check the results.
This chapter describes the testing scheme, modeling methods, and
comparison of results from both active and passive circuits.
The following instruments were used to take measurements:
1. LCR Meter : Low frequency capacitance and inductance measurements.
2. Vector Network Analyzer (HP 8510 B) : S-parameter (100 MHz - 26.5 GHz).
3. Voltmeter/Ammeter : Four probe measurements on resistor structures.
4. Tektronix 7104 oscilloscope with S-4 sampling head.
5. Cascade Summit Automatic Probing Station.
Two types of 50 _ probes with 150 µm contact pitch were used
to test all the passive structures - a G-S-G (Ground-Signal-Ground)
probe [Casc83] with a bandwidth of 40 GHz and a six-channel
probe model WPH-763-150 from Cascade Microtech [Casc91]. The G-S-G
probe was used to make S-parameter measurements of 1-port and
2-port structures. The six-channel probe was used to test all
the dc-resistor structures and the high-speed ring oscillators.
Figure 3.1 shows the footprint of both the probes.
A strong emphasis was placed on establishing a testing scheme for the multi-GHz frequency domain. F-RISC/G chips dissipate, on an average, as much as 12 W in an area of approximately 100 mm2 [Garg94]. The really dense parts of the chips such as the register file, cache block, and custom adder consume more than the average power. Since the HSCD fabrication run had a few of these dense circuits too on the reticle, the probe system was fitted with an off-the-shelf, 62 mm x 62 mm, thermo-electric cooler (TEC) (Part CP 2-127-10L [Eem95]) to provide controlled cooling [Shog94]. A hole was drilled into the middle of the cooler to make a path for the vacuum and the cooler was sealed from the sides using an inexpensive resin. The schematic of the apparatus is shown in Figure 3.2. A simple schematic of the test setup is given in Figure 3.3
The wafer was divided into a 5x5 reticle configuration, as shown in Figure 3.4. This provided about twenty one complete sites out of a total of twenty five. Each site had two copies of the test chip, containing 46 test structures each. The sites shown with a solid border were sampled to provide adequate information about the data variation.
A number of commercial and in-house CAD tools were used to design
the structures and extract the parasitics. The most common packages
were - Compass Design Automation Tools, QuickCap[Leco94], OEA
METAL [Oea94], PSPICE, and MATLAB. Compass design automation tools
were used to layout the structures. Both finite element -METAL,
and monte-carlo - QuickCap, based extractors were used to extract
capacitance from the passive test structures while only QuickCap
was employed to extract capacitance from the active structures.
Empirical formulae [Saku83] based on geometry based heuristics
were not found to be suitable as 3-D fringing effects are not
determined accurately from them. PSPICE was used for circuit simulation
and MATLAB was used to fit numerical models to the measured results.
The capacitors and the pads were modeled as series RLC elements
as shown in Figure 3.5. Rp, Lp, and Cp
are the resistance, inductance, and capacitance, respectively
of the pad structure. These pad parasitics were calculated by
measuring the S-parameters across an open pad structure and numerically
fitting an RLC network to it. This network was then substituted
into a capacitor structure and parameters numerically fitted to
obtain the R, L, and C values for the capacitors.
The S11 parameters of the network given in Figure 3.5 can be expressed in terms of the input impedance of the network (Z) and the impedance of the measurement system (Z0) as
Here, Z0 = 50 . Therefore, Z can be calculated from
measuring S11 parameters. For de-embedding the probes,
S11 is measured across three structures: short, open,
and a load. These measurements provide the value of Rp,
Lp, and Cp. Rstr, Lstr,
and Cstr are determined by numerical fitting.
The measured results are given in Table 3-1. The measured capacitance was as much as 10% lower than the extracted values as given in Table 3-2. The capacitance can simply be given by
where, nitride = 6.8, and Cfringe is the
fringe capacitance which was less than 1% for such capacitors
due to a large area to periphery ratio. This indicated either
a reduced permittivity or an increased thickness of the silicon
Figure 3.6: Measured vs. estimated
capacitance for cap4pf (on left) and cap8pf (on right) (wafer
The measured results for these capacitors from 7 wafers are tabulated in Table 3-3. The extracted capacitance was as much as 50% higher than the predicted values as shown in Table 3-4 and Figure 3.7. The capacitance was calculated, assuming negligible fringing, as following:
where,, [3. 5]
This result, coupled with the results from MIM capacitors, indicated
a number of possibilities which are discussed later.
Figure 3.7: Measured vs. estimated capacitance for the three parallel plate capacitors (wafer8).
The measured and extracted results for these structures are in
Table 3-5 for 7 wafers. The extracted values were obtained by
QuickCap using a process technology file with nominal dielectric
constants and layers thicknesses specified in the design manual.
The differences in these values necessitated a change in the process
technology file. These changes are discussed later.
The measured results of the resistor structures are summarized
in Table 3-6. All the sheet resistances are in agreement with
design manual specifications except the WSiN resistors. Measurements
1 and 2 show that any connection through a collector increases
resistance. From measurements 3 and 4, M2 has a higher sheet resistance
when drawn orthogonally on top of M1 wires. Measurements 3, 4,
and 5 show that M2 sheet resistance increases with Via12 in the
path. Measurements 7 and 9 indicate that M3 sheet resistance goes
up if it is drawn orthogonally on top of M2 wires.
|M1||0.062||0.00057||thru collector contacts|
|M2||0.0176||0.00033||orthogonally loaded by M1|
|M2||0.0190||0.00038||maximally loaded Via 12|
|M3||0.0145||0.00012||orthogonally loaded by M1|
|M3||0.0159||0.00022||orthogonally loaded by M2|
|M3||0.0144||0.00011||on top of devices|
|M3||0.0152||0.00017||maximally loaded Via 23|
|Via 23||0.004 ohms/via|
All the capacitor measurements are summarized in Table 3-7. There
was considerable difference in the parallel plate capacitors and
the crossover capacitors. From resistor structures it was clear
that metal thicknesses were on target and so were the line widths.
So the variation should have been explained by a variation in
dielectric thickness and its permittivity.
The measurements on MIM and parallel plate capacitors indicated
a mismatch between the process technology file used for extraction
and the design rule manual in either the thickness of the intervening
insulator layers or the permittivity of those layers or both.
Rockwell did a SEM measurement on an M1-M2 crossover structure
and found the polyimide thickness was reduced by 40%. The M1-M2
and M2-M3 dielectric thicknesses were reduced in the technology
file to account for this result and all the capacitors were extracted
again. The corrected values are given in Table 3-8 and show some
variation left in the finger and crossover capacitors. The large
difference in M1-M3 crossover capacitor values is due to the planar
nature of the model for the extractor which increased the thickness
of the polyimide layer by the thickness of the M2 layer even though
there was no M2 present in the structure.
|finm1str||0.839 1.3%||0.796 0.5%||5.4%|
|finm2str||0.792 0.5%||0.750 0.5%||5.6%|
|xovrm1m2str1||1.907 2.5%||1.790 0.5%||6.5%|
|xovrm1m2str2||2.318 0.6%||2.114 0.5%||9.6%|
|xovrm2m3str1||1.896 1.9%||1.568 0.5%||20.9%|
|xovrm1m3str1||1.830 1.0%||1.428 0.5%||28.1%|
The M1 finger capacitors values depend on the lateral dielectric
constant of the polyimide and the thickness of the SiO2
layer between the GaAs substrate and M1. It was not possible to
match the finger capacitor values and the M1-M2 crossover capacitors
simultaneously without an assumption of polyimide being anisotropic
in nature with a different vertical and lateral dielectric constants.
Polyimide dielectric constant is typically higher by 20%-25% in
horizontal direction than in the vertical direction as shown in
Table 3-9 [Herm91][Shic96].
|PMDA/ODA DuPont 2550||3.2 (vert.) 3.84 (inplane)|
|BPDA/PPD DuPont 2611||2.6 (vert.) 3.4 (inplane)|
|BPDA/PDA||3.0 (vert.) 3.8 (inplane) [Herm91]|
|PI 2610||2.9-3.5 (vert.) [Sing96]|
|Low stress PI||2.9(z) - 3.4 (xy) [Serg95]|
Commercially available extractors assume isotropic dielectric to solve circuit related Laplace equations. These solvers can be used to solve uniaxial anisotropy problems, where one axis is in the plane of wave propagation, by applying simple transforms [Szen76] [Kita83]. Specifically, when [3. 6]
where z is perpendicular to direction of propagation, the effective dielectric constant of an equivalent isotropic layer is given as
with all the vertical dimensions in the anisotropic layer scaled by a factor
Using this transform and changing the dielectric constant of the
polyimide to 3.2 (vertical) and 4.0 (lateral), the match shown
in Table 3-10 was obtained. The equivalent isotropic dielectric
constant in this case is 3.58 with about 25% anisotropy. The capacitance
of the M1-M3 crossover structure is still low due to a planar
|finm1str||0.839 1.3%||0.839 1.7%||-0.0%|
|finm2str||0.792 0.5%||0.784 1.7%||-1.0%|
|xovrm1m2str1||1.907 2.5%||1.901 1.3%||0.3%|
|xovrm1m2str2||2.318 0.6%||2.299 1.4%||0.8%|
|xovrm2m3str1||1.896 1.9%||1.863 1.8%||1.7%|
|xovrm1m3str1||1.830 1.0%||1.587 1.9%||15.3%|
Each ring oscillator stage was modeled by adding a capacitor at
the output of each stage as the load, as shown in Figure 3.9.
The value of this capacitor was extracted from the layout of the
appropriate oscillator structure.
There are two ways to model the load on a wire in a SPICE-like
circuit simulator as shown in Figure 3.10. The coupling capacitance
between a wire pair is shown as present between the two signal
nodes in the model on the left side. On right side this capacitance
is combined with the node capacitance and is doubled before adding
it to a node. The factor of two comes from a circuit analysis
of odd-mode balanced excitation when the two signals are moving
in the opposite direction with equal amplitude and rise time called
Miller effect. This coupling capacitance becomes significant for
technologies where ground is far away such as GaAs and SOI. Though
the model on the left side is advantageous in terms of its capability
to simulate a non-balanced excitation when the rise times on the
two nodes are not the same. This can happen when one node sees
more coupling capacitance then the other.
The frequency of the ring oscillators were measured in addition to supply voltage, current, and internal voltage swings. A special circuit was designed to calibrate the oscillator structures and measure temperature. The schematic of this sensor is shown in Figure 3.11. The transistor Q0 and Q2 are always ON and Q1 is always OFF. It is biased to carry the same current as the nearby oscillators with 250 mV nominal swing. During measurements, the power-supply voltage is adjusted to observe a 250 mV swing across IS and VS. This is followed by actual oscillator measurements assuming that all the nearby structures had the same collector current due to a similar current load. Since the diode characteristics are very sensitive to temperature, the actual wafer temperature can be easily calculated using previously calibrated Vbe versus temperature characteristics [Whit93].
The oscillation period of twenty-five different types of 8-stage ring oscillators was simulated in SPICE using the design manual based device and interconnect models. The plots of the measured vs. simulated oscillation periods is shown in Figure 3.12. A good agreement between the two values would have put all the points near the equal delay line drawn at 45 angle. The measured period is more than the simulated period suggesting a variation in the device and/or interconnect model. A good match was obtained with the new anisotropic interconnect and slower device models as shown in Figure 3.13. A summary of the measured oscillation periods with the simulated values using different capacitance models is given in Table 3-11.
Figure 3.12: Measured delay vs.
simulated delay for the 25 ring oscillators where the simulated
delays are based on the design manual based device and interconnect
Figure 3.13: Measured delay vs.
simulated delay for the 25 ring oscillators where the simulated
delays are based on a 33 GHz device and the anisotropic interconnect
Figure 3.14 and Figure 3.15 show the observed oscillator output
at minimum and typical heavy loads respectively.
|Oscillator||Load [fF]||Meas||Sim original||Diff.||Sim(33C=1.4||Diff.||Sim aniso||Diff|
|ldro1||M1 (Width = 2, Spacing = 4)|
|ldro2r||M1 loaded with solid M2|
|ldro2l||M1 loaded with solid M3|
|ldro3r||M1 loaded with M2 fingers|
|ldro3l||M1 loaded with M3 fingers|
|ldro5l||M2 (Width = 3, Spacing = 3)|
Note: The measured periods have been averaged over two measurements.
The individual periods differed by up to 5%.
Table 3-11 shows that unloaded ring oscillators are slow by about 35%. Hence the HBT device had an unexpected behavior, exclusive of the previously discussed interlevel dielectric thickness control problem. The first indicators of a problem were found on the first RPI test chip fabricated in 1992 [Phil93]. For that run Rockwell provided S-parameter measurement of a standard HBT. A program was developed by Hans Greub to fit SPICE parameters to this data by using SPICE to simulate the generation of the S-parameter data, whereupon a direct comparison could be made to the measurements. Even though the bias point on the collector emitter voltage in the Rockwell S-parameter measurement was not ideal for our circuit's range of operation, it could be determined that the transistor behaved as if it had a 33% lower transit time frequency at all collector current values. Since the plot of this frequency for various collector currents is inversely proportional to the total base capacitance of the HBT, this implied that the base capacitance was 33% larger than the SPICE model provided in the Rockwell design manual.
Figure 3.16 and Figure 3.17 compare the magnitude of S21
parameter on devices from this test run, measured at Mayo, with
S-parameters of different device models. The measured S21
parameters which are an indicator of the gain and bandwidth of
the device are compared with the S21 of the device
model in the design manual (S21_q1_dm) , a new switching device
model (S1_q1_sw) and the 33 GHz model extracted from the old testchip
(S1_q1_33). The measured S-parameters match the design manual
model quite well at currents levels (2.1 mA) where the device
reaches optimal ft..
However, in switching applications, the devices are turned on and off. Hence, max ft is not relevant, but how quickly the device turns on or off is relevant. The turn-on characteristics of the device are most important for the switching time since the device spends most of the switching transient in the low current regime and the device is much slower at low current than at high current levels. This correspond to the ft or S21 parameters at low current levels. Figure 3.17 shows that the measured S-parameters on the first test chip are much lower than predicted by any model at low current levels (0.4 mA).
The design-simulation-measurement-correlation cycle in this effort provided the much needed confidence in an evolving technology and helped in formulating a circuit design guide for later designs. This effort also succeeded in the design of a set of test structures for future fabrication runs for much more complex designs. The whole process brought forth issues missed by earlier test attempts. Major observations are as follows
_ The model does not correctly model the turn-on characteristics of the HBT device. A model for switching applications must very accurately model the ft at low currents and not just ft near the optimal collector current and VCE0 that gets quoted. As shown in Figure 3.18 the model ft rises very sharply to its maximum value at low current levels while the measured devices showed maximum ft at high current levels only.
One shortcoming of the testchip was the absence of long wires in the ring oscillator structures which resulted in missing the RC transmission line effect. The results from the test chip were applied to F-RISC/G chips in the following manner