CHAPTER 3

TEST CHIP - TESTING, MODELING, AND RESULTS

Introduction

The test chip was fabricated at Rockwell International during the Fall of 1994 and both wafers and lapped reticles were received at Rensselaer in December 1994. S-parameter measurements on all the capacitors and devices were done at Rockwell. The ring oscillators and the resistor structures were tested at Rensselaer. A few measurements were also repeated outside Rensselaer to double check the results. This chapter describes the testing scheme, modeling methods, and comparison of results from both active and passive circuits.

Test Scheme

The following instruments were used to take measurements:

1. LCR Meter : Low frequency capacitance and inductance measurements.

2. Vector Network Analyzer (HP 8510 B) : S-parameter (100 MHz - 26.5 GHz).

3. Voltmeter/Ammeter : Four probe measurements on resistor structures.

4. Tektronix 7104 oscilloscope with S-4 sampling head.

5. Cascade Summit Automatic Probing Station.

Probing Scheme

Two types of 50 _ probes with 150 µm contact pitch were used to test all the passive structures - a G-S-G (Ground-Signal-Ground) probe [Casc83] with a bandwidth of 40 GHz and a six-channel S-S-P-G-S-S-G-P-S-S (Signal-Signal-Power-Ground-Signal-Signal-Ground-Power-Signal-Signal) probe model WPH-763-150 from Cascade Microtech [Casc91]. The G-S-G probe was used to make S-parameter measurements of 1-port and 2-port structures. The six-channel probe was used to test all the dc-resistor structures and the high-speed ring oscillators. Figure 3.1 shows the footprint of both the probes.

(a)

(b)

Figure 3.1: (a) GSG and (b) Multi-channel probe tips.

Test Fixture and Testing Strategy

A strong emphasis was placed on establishing a testing scheme for the multi-GHz frequency domain. F-RISC/G chips dissipate, on an average, as much as 12 W in an area of approximately 100 mm2 [Garg94]. The really dense parts of the chips such as the register file, cache block, and custom adder consume more than the average power. Since the HSCD fabrication run had a few of these dense circuits too on the reticle, the probe system was fitted with an off-the-shelf, 62 mm x 62 mm, thermo-electric cooler (TEC) (Part CP 2-127-10L [Eem95]) to provide controlled cooling [Shog94]. A hole was drilled into the middle of the cooler to make a path for the vacuum and the cooler was sealed from the sides using an inexpensive resin. The schematic of the apparatus is shown in Figure 3.2. A simple schematic of the test setup is given in Figure 3.3

Figure 3.2: Schematic of the test jig.

The wafer was divided into a 5x5 reticle configuration, as shown in Figure 3.4. This provided about twenty one complete sites out of a total of twenty five. Each site had two copies of the test chip, containing 46 test structures each. The sites shown with a solid border were sampled to provide adequate information about the data variation.

Figure 3.3: Schematic of the testing configuration.

Figure 3.4: Distribution of test sites over the wafer.

Results and Discussion

Extraction Software

A number of commercial and in-house CAD tools were used to design the structures and extract the parasitics. The most common packages were - Compass Design Automation Tools, QuickCap[Leco94], OEA METAL [Oea94], PSPICE, and MATLAB. Compass design automation tools were used to layout the structures. Both finite element -METAL, and monte-carlo - QuickCap, based extractors were used to extract capacitance from the passive test structures while only QuickCap was employed to extract capacitance from the active structures. Empirical formulae [Saku83] based on geometry based heuristics were not found to be suitable as 3-D fringing effects are not determined accurately from them. PSPICE was used for circuit simulation and MATLAB was used to fit numerical models to the measured results.

Passive Structures

Capacitor Model

The capacitors and the pads were modeled as series RLC elements as shown in Figure 3.5. Rp, Lp, and Cp are the resistance, inductance, and capacitance, respectively of the pad structure. These pad parasitics were calculated by measuring the S-parameters across an open pad structure and numerically fitting an RLC network to it. This network was then substituted into a capacitor structure and parameters numerically fitted to obtain the R, L, and C values for the capacitors.

Figure 3.5: Model of a capacitor and the pads.

The S11 parameters of the network given in Figure 3.5 can be expressed in terms of the input impedance of the network (Z) and the impedance of the measurement system (Z0) as

[3. 1]

[3. 2]

Here, Z0 = 50 . Therefore, Z can be calculated from measuring S11 parameters. For de-embedding the probes, S11 is measured across three structures: short, open, and a load. These measurements provide the value of Rp, Lp, and Cp. Rstr, Lstr, and Cstr are determined by numerical fitting.

MIM Capacitors

The measured results are given in Table 3-1. The measured capacitance was as much as 10% lower than the extracted values as given in Table 3-2. The capacitance can simply be given by

[3. 3]

where, nitride = 6.8, and Cfringe is the fringe capacitance which was less than 1% for such capacitors due to a large area to periphery ratio. This indicated either a reduced permittivity or an increased thickness of the silicon nitride layer.

Table 3-1: Capacitance measurement results from 7 wafers.

Structure
Number of

Sites Averaged
MaxValue

[pF] (wafer#)
Min Value

[pF] (wafer#)
Average

Capacitance [pF]
cap4pf
70
2.297 (w1)
1.787 (w1)
1.941 4.8%
cap8pf
71
8.827 (w2)
7.513 (w2)
7.551 4.5%

Table 3-2: Difference between measured and extracted capacitances.

Structure
Extracted

Capacitance[pF]
Measured

Capacitance[pF]
Diff.
cap4pf
2.080
1.941 ± 4.8%
-6.7 %
cap8pf
8.320
7.551 ± 4.5%
-9.2 %

Figure 3.6: Measured vs. estimated capacitance for cap4pf (on left) and cap8pf (on right) (wafer 8).

Parallel Plate Capacitors

The measured results for these capacitors from 7 wafers are tabulated in Table 3-3. The extracted capacitance was as much as 50% higher than the predicted values as shown in Table 3-4 and Figure 3.7. The capacitance was calculated, assuming negligible fringing, as following:

[3. 4]

where,, [3. 5]

This result, coupled with the results from MIM capacitors, indicated a number of possibilities which are discussed later.

Table 3-3 : Capacitance measurements results from 7 wafers.

Structure
Number of

Sites Averaged
MaxValue

[pF] (wafer#)
Min Value

[pF] (wafer#)
Average

Capacitance[pF]
capm1m21
72
1.967 (w1)
1.556 (w1)
1.701 5.3%
capm1m22
54
3.426 (w3)
2.994 (w3)
3.245 4.5%
capm1m24
64
8.648 (w1)
7.011 (w1)
7.576 5.1%

Table 3-4: Difference between measured and extracted capacitances.

Structure
Extracted

Capacitance[pF]
Measured

Capacitance[pF]
Diff.
capm1m21
1.09
1.701 ± 5.3%
56.0 %
capm1m22
2.18
3.245 ± 4.5%
48.8 %
capm1m24
5.18
7.576 ± 5.1%
46.2 %

Figure 3.7: Measured vs. estimated capacitance for the three parallel plate capacitors (wafer8).

Finger and Crossover Capacitors

The measured and extracted results for these structures are in Table 3-5 for 7 wafers. The extracted values were obtained by QuickCap using a process technology file with nominal dielectric constants and layers thicknesses specified in the design manual. The differences in these values necessitated a change in the process technology file. These changes are discussed later.

Table 3-5 : Capacitance measurements results from 7 wafers.

Structure
Number

of Sites Averaged
Max

[pF] (wafer#)
Min

[pF] (wafer#)
Measured

Capacitance [pF]
Extracted

Capacitance [pF]
Diff.
finm1str
75
1.027(3)
0.808(3)
0.8391.3%
0.700
19.8%
finm2str
72
0.898(8)
0.781(8)
0.7920.5%
0.630
25.7%
xovrm1m2str1
58
2.282(3)
1.843(3)
1.9072.5%
1.271
50.0%
xovrm1m2str2
59
2.652(1)
2.275(1)
2.3180.6%
1.886
22.9%
xovrm2m3str1
65
2.156(8)
1.859(8)
1.8961.9%
1.076
76.2%
xovrm1m3str1
54
2.071(3)
1.800(3)
1.8301.0%
1.102
66.0%

Resistors

The measured results of the resistor structures are summarized in Table 3-6. All the sheet resistances are in agreement with design manual specifications except the WSiN resistors. Measurements 1 and 2 show that any connection through a collector increases resistance. From measurements 3 and 4, M2 has a higher sheet resistance when drawn orthogonally on top of M1 wires. Measurements 3, 4, and 5 show that M2 sheet resistance increases with Via12 in the path. Measurements 7 and 9 indicate that M3 sheet resistance goes up if it is drawn orthogonally on top of M2 wires.

Figure 3.8: Resistance measurement setup.

Table 3-6: Interconnect sheet resistance measurements.

No
Resistor Type
Meas Sheet R [ohms/sq]
Est Sheet R [ohms/sq]
Mean
Std. Dev.
Mean
Std. Dev.
1
M1 0.0550.00039
0.055
0.0036
2
M1 0.0620.00057thru collector contacts
3
M20.0173 0.00019
0.025
0.0020
4
M20.0176 0.00033orthogonally loaded by M1
5
M20.0190 0.00038maximally loaded Via 12
6
Via12 0.00039 ohms/via
7
M30.0144 0.00012
0.015
0.0004
8
M30.0145 0.00012orthogonally loaded by M1
9
M30.0159 0.00022orthogonally loaded by M2
10
M3 0.01440.00011on top of devices
11
M3 0.01520.00017maximally loaded Via 23
12
Via 23 0.004 ohms/via
13
NiCr 48.9851.768
51.4
1.4
14
WSiN 253.514.13
290.5
8.23

Discussion about Interconnect Structure

All the capacitor measurements are summarized in Table 3-7. There was considerable difference in the parallel plate capacitors and the crossover capacitors. From resistor structures it was clear that metal thicknesses were on target and so were the line widths. So the variation should have been explained by a variation in dielectric thickness and its permittivity.

Table 3-7: Comparison of measured and expected capacitances.

Structure
Type
Measured [pF]
Extracted [pF]
Difference
cap4pf
MIM (M1/M2)
1.941
2.080
-6.7 %
cap8pf
MIM (M1/M2)
7.551
8.320
-9.2 %
capm1m21
Parallel (M1/M2)
1.701
1.090
56.0 %
capm1m22
Parallel (M1/M2)
3.245
2.180
48.8 %
capm1m24
Parallel (M1/M2)
7.576
5.180
46.2 %
finm1str
Finger (M1/M1)
0.839
0.700
19.8%
finm2str
Finger (M1/M1)
0.792
0.630
25.7%
xovrm1m2str1
Crossover(M1/M2)
1.907
1.271
50.0%
xovrm1m2str2
Crossover(M1/M2)
2.318
1.886
22.9%
xovrm2m3str1
Crossover(M2/M3)
1.896
1.076
76.2%
xovrm1m3str1
Crossover(M1/M3)
1.830
1.102
66.0%

The measurements on MIM and parallel plate capacitors indicated a mismatch between the process technology file used for extraction and the design rule manual in either the thickness of the intervening insulator layers or the permittivity of those layers or both. Rockwell did a SEM measurement on an M1-M2 crossover structure and found the polyimide thickness was reduced by 40%. The M1-M2 and M2-M3 dielectric thicknesses were reduced in the technology file to account for this result and all the capacitors were extracted again. The corrected values are given in Table 3-8 and show some variation left in the finger and crossover capacitors. The large difference in M1-M3 crossover capacitor values is due to the planar nature of the model for the extractor which increased the thickness of the polyimide layer by the thickness of the M2 layer even though there was no M2 present in the structure.

Table 3-8: Comparison of measured and extracted capacitance values with thinned dielectric.

Structure Name
Measured Capacitance [pF]
Extracted Capacitance [pF]
Difference
finm1str0.839 1.3%0.796 0.5% 5.4%
finm2str0.792 0.5%0.750 0.5% 5.6%
xovrm1m2str11.907 2.5% 1.790 0.5%6.5%
xovrm1m2str22.318 0.6% 2.114 0.5%9.6%
xovrm2m3str11.896 1.9% 1.568 0.5%20.9%
xovrm1m3str11.830 1.0% 1.428 0.5%28.1%

The M1 finger capacitors values depend on the lateral dielectric constant of the polyimide and the thickness of the SiO2 layer between the GaAs substrate and M1. It was not possible to match the finger capacitor values and the M1-M2 crossover capacitors simultaneously without an assumption of polyimide being anisotropic in nature with a different vertical and lateral dielectric constants. Polyimide dielectric constant is typically higher by 20%-25% in horizontal direction than in the vertical direction as shown in Table 3-9 [Herm91][Shic96].

Table 3-9: Dielectric constants of common polyimides.

DielectricDielectric Constant
PMDA/ODA DuPont 25503.2 (vert.) 3.84 (inplane)
BPDA/PPD DuPont 26112.6 (vert.) 3.4 (inplane)
BPDA/PDA 3.0 (vert.) 3.8 (inplane) [Herm91]
PI 26102.9-3.5 (vert.) [Sing96]
Low stress PI2.9(z) - 3.4 (xy) [Serg95]

Commercially available extractors assume isotropic dielectric to solve circuit related Laplace equations. These solvers can be used to solve uniaxial anisotropy problems, where one axis is in the plane of wave propagation, by applying simple transforms [Szen76] [Kita83]. Specifically, when [3. 6]

where z is perpendicular to direction of propagation, the effective dielectric constant of an equivalent isotropic layer is given as

[3. 7]

with all the vertical dimensions in the anisotropic layer scaled by a factor

[3. 8]

Using this transform and changing the dielectric constant of the polyimide to 3.2 (vertical) and 4.0 (lateral), the match shown in Table 3-10 was obtained. The equivalent isotropic dielectric constant in this case is 3.58 with about 25% anisotropy. The capacitance of the M1-M3 crossover structure is still low due to a planar model.

Table 3-10: Comparison of measured and extracted capacitance values (anisotropic).

Structure Name
Measured Capacitance [pF]
Extracted Capacitance [pF]
Difference
finm1str0.839 1.3%0.839 1.7% -0.0%
finm2str0.792 0.5%0.784 1.7% -1.0%
xovrm1m2str11.907 2.5% 1.901 1.3%0.3%
xovrm1m2str22.318 0.6% 2.299 1.4%0.8%
xovrm2m3str11.896 1.9% 1.863 1.8%1.7%
xovrm1m3str11.830 1.0% 1.587 1.9%15.3%

Active Structures

Ring Oscillator Model

Each ring oscillator stage was modeled by adding a capacitor at the output of each stage as the load, as shown in Figure 3.9. The value of this capacitor was extracted from the layout of the appropriate oscillator structure.

Figure 3.9: Model of a single oscillator stage.

Figure 3.10: Differential wire capacitance and its equivalent model.

There are two ways to model the load on a wire in a SPICE-like circuit simulator as shown in Figure 3.10. The coupling capacitance between a wire pair is shown as present between the two signal nodes in the model on the left side. On right side this capacitance is combined with the node capacitance and is doubled before adding it to a node. The factor of two comes from a circuit analysis of odd-mode balanced excitation when the two signals are moving in the opposite direction with equal amplitude and rise time called Miller effect. This coupling capacitance becomes significant for technologies where ground is far away such as GaAs and SOI. Though the model on the left side is advantageous in terms of its capability to simulate a non-balanced excitation when the rise times on the two nodes are not the same. This can happen when one node sees more coupling capacitance then the other.

Results

The frequency of the ring oscillators were measured in addition to supply voltage, current, and internal voltage swings. A special circuit was designed to calibrate the oscillator structures and measure temperature. The schematic of this sensor is shown in Figure 3.11. The transistor Q0 and Q2 are always ON and Q1 is always OFF. It is biased to carry the same current as the nearby oscillators with 250 mV nominal swing. During measurements, the power-supply voltage is adjusted to observe a 250 mV swing across IS and VS. This is followed by actual oscillator measurements assuming that all the nearby structures had the same collector current due to a similar current load. Since the diode characteristics are very sensitive to temperature, the actual wafer temperature can be easily calculated using previously calibrated Vbe versus temperature characteristics [Whit93].

Figure 3.11: Schematic of the voltage/current/temperature sensor.

The oscillation period of twenty-five different types of 8-stage ring oscillators was simulated in SPICE using the design manual based device and interconnect models. The plots of the measured vs. simulated oscillation periods is shown in Figure 3.12. A good agreement between the two values would have put all the points near the equal delay line drawn at 45 angle. The measured period is more than the simulated period suggesting a variation in the device and/or interconnect model. A good match was obtained with the new anisotropic interconnect and slower device models as shown in Figure 3.13. A summary of the measured oscillation periods with the simulated values using different capacitance models is given in Table 3-11.

Figure 3.12: Measured delay vs. simulated delay for the 25 ring oscillators where the simulated delays are based on the design manual based device and interconnect models.

Figure 3.13: Measured delay vs. simulated delay for the 25 ring oscillators where the simulated delays are based on a 33 GHz device and the anisotropic interconnect models.

Figure 3.14 and Figure 3.15 show the observed oscillator output at minimum and typical heavy loads respectively.

Figure 3.14 : Ring oscillator waveform (2.42 GHz) - minimum load.

Figure 3.15: Ring oscillator waveform (798 MHz) - heavy M2 loading.

Table 3-11: Comparison of measured and simulated oscillator delays.

OscillatorLoad [fF] MeasSim original Diff.Sim(33C=1.4Diff. Sim anisoDiff
ldro1M1 (Width = 2, Spacing = 4)
period(u)86 812570-29.8% 8383.20%811 -0.12%
period(v)180 1180.5825-30.1% 12008.42%1158 -1.88%
period(w)229 1368.5947-21.4% 13600.62%1335 -2.41%
period(x)281 1547.51087-29.7% 15701.45%1524 -1.50%
ldro2rM1 loaded with solid M2
period(u)99 895603-32.6% 886-0.01%898 0.39%
period(v)211 1385.5900-35.0 1306-5.73%1381 -0.33%
period(w)266 1640.51058-35.5% 1520-7.34%1620 -1.22%
period(x)328 19041209-36.5% 1740-8.61%1883 -1.12%
ldro2lM1 loaded with solid M3
period(u)84 836.5567-32.2% 834-0.29%825 -1.37%
period(v)188 1204841-30.1% 12211.41%1184 -1.63%
period(w)234 1430.5966-32.4% 1390-2.83%1376 -3.81%
period(x)283 1619.51090-32.6% 1574-2.8%1577 -2.63%
ldro3rM1 loaded with M2 fingers
period(u)94 875595-32% 873-0.22%881 0.66%
period(v)203 1336876-34.4% 1271-4.86%1302 -2.57%
period(w)255 1563.51027-34.3% 1476-5.59%1527 -2.32%
period(x)310 1791.51169-34.7% 1684-6.00%1754 -2.04%
ldro3lM1 loaded with M3 fingers
period(u)87 810.5573-29.3% 8423.88%828 2.12%
period(v)187 1203.5844-29.8% 12261.86%1190 -1.15%
period(w)233 1413.5970-31.3% 1396-1.23%1389 -1.70%
period(x)286 16091105-31.3% 15940.93%1572 -2.29%
ldro5lM2 (Width = 3, Spacing = 3)
period(u)73 778.5534-31.4% 7860.96%785 0.86%
period(v)156 1086764-29.6% 11041.63%1096 0.98%
period(w)200 1245875-29.7% 12702.0%1249 0.35%
period(x)238 1390.5980-29.5% 14171.90%1417 1.90%
ldro5runloaded ringosc
period(u)14 549354-35.5% 540-1.63%556 1.35%

Note: The measured periods have been averaged over two measurements. The individual periods differed by up to 5%.

Device Switching Performance

Table 3-11 shows that unloaded ring oscillators are slow by about 35%. Hence the HBT device had an unexpected behavior, exclusive of the previously discussed interlevel dielectric thickness control problem. The first indicators of a problem were found on the first RPI test chip fabricated in 1992 [Phil93]. For that run Rockwell provided S-parameter measurement of a standard HBT. A program was developed by Hans Greub to fit SPICE parameters to this data by using SPICE to simulate the generation of the S-parameter data, whereupon a direct comparison could be made to the measurements. Even though the bias point on the collector emitter voltage in the Rockwell S-parameter measurement was not ideal for our circuit's range of operation, it could be determined that the transistor behaved as if it had a 33% lower transit time frequency at all collector current values. Since the plot of this frequency for various collector currents is inversely proportional to the total base capacitance of the HBT, this implied that the base capacitance was 33% larger than the SPICE model provided in the Rockwell design manual.

Figure 3.16 and Figure 3.17 compare the magnitude of S21 parameter on devices from this test run, measured at Mayo, with S-parameters of different device models. The measured S21 parameters which are an indicator of the gain and bandwidth of the device are compared with the S21 of the device model in the design manual (S21_q1_dm) , a new switching device model (S1_q1_sw) and the 33 GHz model extracted from the old testchip (S1_q1_33). The measured S-parameters match the design manual model quite well at currents levels (2.1 mA) where the device reaches optimal ft..

Figure 3.16: Measured vs. modeled S21 parameters at IC = 2.1 mA and VCE = 2 V.

However, in switching applications, the devices are turned on and off. Hence, max ft is not relevant, but how quickly the device turns on or off is relevant. The turn-on characteristics of the device are most important for the switching time since the device spends most of the switching transient in the low current regime and the device is much slower at low current than at high current levels. This correspond to the ft or S21 parameters at low current levels. Figure 3.17 shows that the measured S-parameters on the first test chip are much lower than predicted by any model at low current levels (0.4 mA).

Figure 3.17: Measured vs. modeled S21 parameters at IC = 0.4 mA and VCE = 2.0 V.

Conclusions

The design-simulation-measurement-correlation cycle in this effort provided the much needed confidence in an evolving technology and helped in formulating a circuit design guide for later designs. This effort also succeeded in the design of a set of test structures for future fabrication runs for much more complex designs. The whole process brought forth issues missed by earlier test attempts. Major observations are as follows

_ The model does not correctly model the turn-on characteristics of the HBT device. A model for switching applications must very accurately model the ft at low currents and not just ft near the optimal collector current and VCE0 that gets quoted. As shown in Figure 3.18 the model ft rises very sharply to its maximum value at low current levels while the measured devices showed maximum ft at high current levels only.

One shortcoming of the testchip was the absence of long wires in the ring oscillator structures which resulted in missing the RC transmission line effect. The results from the test chip were applied to F-RISC/G chips in the following manner

Figure 3.18: Ft vs. IC for the theoretical and actual devices at given bias.