Appendix B

A New Register File Design

The fabricated register file access speed was measured to be at least 500 ps. Insufficient yield in the experimental process prevented testing at higher speed. But speed tests of other circuits in the test chip indicated lower speed than predicted by the SPICE simulation. Several factors were responsible for the speed hit observed.

The fT of the transistors were around 30 GHz instead of 50 GHz; extra Nitride layer, which has the dielectric constant of 7.5 compared to 3.2 of the Polyimide, was added during the fabrication process; and the capacitance modelling tools, LINPAR and Magicad, predicted lower capacitance compared to the results of QUICKCAD and the 3-D modelling tool recently made available to our group.

New SPICE simulation with the new layout capacitances predicted by QUICKCAD of the fabricated register file design yielded an access time of 240 ps. The interconnect capacitances of some of the key nodes have increased by as much as six fold. For 1 GHz version of the F-RISC/G, register file needs to have an access time of under 200 ps.

SPICE simulation indicates the following changes on the register file design results in the desired access time: change the metal layers that are routed on level 2 to level 3 to reduce the parasitic capacitance load (the level 3 metal layer was not available during the first fabrication run); increase the bit line driver and the address driver currents.

The new address driver currents through Q5, Q9, and Q12 (Fig. 6.2) have been increased to 17.7 mA and the bit line currents have been increased to 2.39 mA. Consequently, the Q5, Q9, and Q12 have been doubled to prevent transistor burn-out at the new current levels. The decoder resistors, R6 and R7 (Fig. 6.1), on the otherhand, have been halved to maintain the previous word line swing. The decoder current is doubled when the address driver current is doubled.

Similarly, the word line driver transistor, Q12, have been doubled eventhough the bit line current driver transistors have not been (Fig. 6.1); additional increase in the bit line current. Any increase in the bit line current is seen at Q12 multiplied eight times since there are eight memory columns. Since the bit line currents are increased by changing R14 and R15 of Fig. 6.1, corresponding resistors of the threshold generator circuit, R7 and R15 of Fig. 6.5, must also be changed. Also, R1 of the threshold generator circuit has been changed to reflect the decrease in the decoder resistors.

Table B.1. Parameters of the new register file design

Number of Transistors


Register File Size

1 mm ´ 2 mm

Maximum Q1 Current

2.4 mA

Maximum Q3 Current

16 mA

Power Dissipation

1.7 W

Power Supply

-5.2 V

Simulated Access Time

193 ps

The SPICE simulation results of the new register file design is shown in Fig. B.1. The new access time is about 193 ps and is within the target time of under 200 ps. The parameters of the new register file design is summarized in Table. B.1. Table B.2 summarizes currents in the subcircuits of the new register file and Table B.3 summarizes new parasitic capactances of the critical nodes that have been extracted with QUICKCAP. The time slack for the register file read of the F-RISC/G can be calculated to be:

250 ps (one clock phase) - 193 ps (read access time) - 20 ps (address input multiplexer) - 20 ps (data output latch) = 17 ps.

Following design requirements have been observed:

· All currents in Q1 and Q3 are less than or equal to the maximum current specifications (Table B.1).

· No transistor is to be saturated.

· Simulation temerature is at 27 degrees since the device models are only valid at this temerature.

· Memory hold voltage is to be greater than or equal to 250 mV.

· Word Line swing is to be greater than or equal to 800 mV static in magnitude.

· Read/Write Threshold voltage must be at 50%-60% of the selected memory cell voltage of the threshold voltage generator circuit.

· One of the base voltages on Q3 and Q11 (Fig. 6.1) must rise at least 80 mV above the highest base voltage of a selected memory cell during a write.

· The output voltages on the OPAMP in the threshold generator must be balanced to within 50 mV.

The simulation plots that show the operation of the register file are contained in figures Fig. B.2 to Fig. B.6. The memory cell and the overall register file layouts are shown in Fig. B.7 and Fig. B.8, respectively.

Table B.2. Subcircuit currents of the register file

Bit Line

2.39 mA


2.25 mA

Memory Select

0.60 mA

Memory Hold

0.37 mA

Sense Amplifier

2.5 mA

Address Line Driver

17.7 mA

Table B.3. Parasitic Capacitances extracted with QUICKCAP

Bit Line

240 fF

Word Line

80 fF

Address Line

425 fF

Sense Amplifier

50 fF

Fig. B.1. SPICE simulation result of the new register file design

Fig. B.2. Memory hold voltage is greater than 250 mV

Fig. B.3. Write pulse rises above the selected memory cells by greater than 80 mV


Fig. B.4. Read/Write Threshold voltage at 50%-60% of the selected memory cell

Fig. B.5. Word Line swing is greater than 800mV in magnitude

Fig. B.6. OPAMP output voltages are less than 50 mV


Fig. B.7. Layout of the memory cell


Fig. B.8. Overall Register File layout