Appendix C

To Change Phase Detector State

The phase detector circuit of Fig. 3.8 includes control circuitry for forcing change in the phase detector state upon detecting the VCDE limit signals; SCHMITT2, SCHMITT3, SR3, and GATEKPR.

During the normal mode of the phase detector operation, UP2 and DOWN2 signals are passed directly to the FILTER by the GATEKPR. At this point, the phase detector has chosen one of the two available lock states. However, when a VCDE limit is detected the phase detector goes into the special mode and switches to the other lock state.

When LOW1 is asserted logic high, then FU3 is also asserted logic high. The GATEKPR then asserts its output logic high, which causes the analog filter output to rise higher. It should be mentioned that the GATEKPR gives FU3 and FD3 signals higher precedent over UP2 and DOWN2 signals. As the filter output rises, the VCDE delays change in opposite direction. Eventually, the delay change will reach a point such that the relationship of the UP2 and DOWN2 signals is reversed. The third Schmitt trigger (SCHMITT2) detects this event and clears appropriate latch (SR3). In the current example, it clears the SR3 latch that has been asserting FU3 signal logic high. When FU3 signal is cleared, the GATEKPR again lets UP2 and DOWN2 signals pass through to the FILTER. The important difference being that the relationship between the UP2 and DOWN2 signals have been reversed and that the phase detector is now guaranteed to lock. Remember, the phase detector has travelled through the other side of its characteristic already.