Appendix D

Key Test Signals

Fig. D.1 shows the expected XOR output (see Clock Test, Phase Test of Fig. 5.1) as the PLL is being locked during the Test Mode as explained in Chapter 5. The figure clearly shows the reduction in amplitudes and widths of the spikes as the skew in the clock signals are reduced. Fig. D.2 shows that the filter output signal responds properly to the changes in the internal VCDE delays after the PLL has been locked. The final skew between the clock signals at the internal delays are shown in Fig. D.3.

Fig. D.1. XOR outputs for different clock skews

Fig. D.2. Filter output response during the lock state to the varying internal VCDE delays

Fig. D.3. Final clock skew at the internal VCDE delays