Chapter 4

Four Clock Phase and SYNC/RESET Generator Circuits

4.1. Clock Phase Generator Circuit

The main function of the clock phase generator circuit for the F-RISC/G is the generation of four periodic clock pulses of equal duration from a master clock of twice the needed frequency. Each of these pulses corresponds to one of the four phases or divisions into which an instruction cycle is divided in the F-RISC/G architecture. Hence, for a 1000 MIPS microprocessor, the nominal pulse duration is 250 ps. SPICE simulations indicate a pulse duration of about 240 ps for the phase generator circuit to be used in the F-RISC/G (Fig. 4.1). The part of the circuit that generates four phases from a master clock is based on [GREUBPAT] with modifications for the differential operation. This circuit generates a pulse at each of the rising and falling edges of the master clock signal with a pulse duration equal to the half of the master clock period; the master clock signal frequency must be twice the desired clock frequency for a clock with four phases. In addition to the architectural requirements of generating four phases, the circuit must adhere to the requirements of the boundary scan testing scheme implemented in the fabricated chips. It must be able to freeze the clock in any phase for an arbitrary duration. The circuit that implements this freeze function is developed and shown in Fig. 4.2. The clock can be frozen after the generation of one clock phase. When the clock is eventually restarted the clock phases must continue from the frozen state. For example, if the clock was frozen during the second phase, the third phase should be generated next instead of the first phase. This would cause desired change in the state of the chip being tested. The functional test can be done by comparing the observed state with the expected ones.

Fig. 4.1. The SPICE simulation of the Clock Phase Generator circuit with the FREEZE signal asserted


In Fig. 4.3 the circuit that generates four phases from the master clock is shown. The circuit that generates the first phase (PHCKT1) is shown in Fig. 4.4 and is slightly different from the circuit for the generation of the second through fourth phases (PHCKT2, PHCKT3, PHCKT4 ) as shown in Fig. 4.5. The main differences between the two circuits are their behaviours when the synchronization (SYNC) signal is logic high. The first clock phase (PHOUT1) is asserted logic high whereas the second through the fourth clock phases (PHOUT2, PHOUT3, and PHOUT4) are asserted logic low. The state of the clock phases remain unchanged until SYNC is asserted logic low, after which the clock phases are generated sequentially.

As the master clock oscillates, Q1_69 and Q1_70 are alternately switched and the current is alternately pulled in ICLK and ICLKB. The ICLK is connected to first and third phases and the ICLKB is connected to second and fourth phases. The VBIN and VBOUT in each of the phase generator circuits are connected in a daisy chain manner.

The current may flow either in the ICLK or the ICLKB, as mentioned before. If it flows in ICLK, this current flows either in Q1_9 (Fig. 4.4) of the PHCKT1 or in Q1_60 (Fig. 4.5) of the PHCKT3. The actual flow depends on which transistor base (VBIN) is at a higher voltage. If the current flows in the ICLKB, this current flows either in Q1_60 (Fig. 4.5) of the PHCKT2 or the PHCKT4.

During the period when the SYNC is at logic high, the VBOUT of the PHCKT1 (VBOUT1) is asserted logic high as are the VBINs of the PHCKT1 and PHCKT2 (VBIN1 and VBIN2). On the otherhand, VBOUT2, VBOUT3, and VBOUT4 are asserted logic low as are the VBIN3 and VBIN4. Immediately following the deassertion of the SYNC to logic low, the VBIN1 and VBIN2 are at higher voltages relative to the VBIN3 and VBIN4, respectively. If at this moment the current flows in the ICLK, this current would flow through Q1_9 of the PHCKT1 causing current to flow in Q1_11 and logic high at the PHOUT1.


Fig. 4.2. The toplevel view of the Clock Phase Generator circuit



Fig. 4.3. The toplevel view of the Four Phase Generator circuit (FPHFOUR)


Fig. 4.4. The first clock phase generator circuit


Fig. 4.5. The second, third, and fourth clock phases generator circuit


During this period the VBIN1, VBIN2, and VBOUT1 are still maintained at logic high. When the master clock change causes current flow in the ICLKB, this current flows in Q1_60 of the PHCKT2 instead of the PHCKT4 since the VBIN2 is at a higher voltage than the VBIN4. The current flow in Q1_60 results in the current flow in Q1_62 of the PHCKT2 and results in logic high of the PHOUT2. Meanwhile, the current no longer flows in Q1_9 of the PHCKT1 and results in the VREFB at higher voltage than the VREF. The current through Q1_11 switches to Q1_1, and the PHOUT1 is asserted logic low.

The next change in the master clock causes Q1_69 to turn on and the current is pulled from the ICLK instead of the ICLKB. Since the VBIN3 is precharged to a higher voltage than the VBIN1 during the previous state, the current flows through Q1_60 of the PHCKT3 instead of Q1_9 of the PHCKT1. Consequently, the VBOUT3 is asserted logic high while the VBOUT2 falls back to logic low. The next change in the master clock asserts the VBOUT4 to logic high and the VBOUT3 to logic low. The next change asserts the VBOUT1 to logic high and the sequence of the clock phase generation has come to a full circle. In essence, the asserted PHCKT prepares the adjacent PHCKT for the coming transition in the master clock through the VBOUT/VBIN connections.

As shown Fig. 4.2, the freeze circuit consists of three major blocks; FPHDLAT, FPHMSLC, and FPHXORA. FPHDLAT is a simple latch circuit as shown in Fig. 4.6. The FPHMSLC is a master-slave latch with a clear as shown in Fig. 4.7. The FPHXORA shown in Fig. 4.8 is a combination of an AND circuit and an Exclusive-OR (XOR) circuit.

When the EN3J1 signal is asserted logic high, the FPHMSLC outputs are eventually asserted logic high. The FPHDLAT becomes transparent and the master clock is directly provided to the FPHFOUR, which genenerates the four phases as described above.

Fig. 4.6. A simple D-Latch circuit in CML logic (FPHDLAT)

Fig. 4.7. A simple master-slave latch in CML logic (FPHMSLC)


Fig. 4.8. A circuit that combines AND and Exclusive-OR functions (FPHXORA)


The initial state of the FPHMSLC output could be at either logic high or logic low. If it is at logic low, the output of the FPHXORA generates write signal resulting in a logic high at the FPHMSLC outputs. The XOR part of the FPHXORA senses master clock and the output of the FPHDLAT. If the EN2J1 is at logic low, one of the XOR is held constant and the XOR reduces either to a buffer or an inverter. Since the other input is the master clock, the output of the XOR is either the master clock or the inversion of it. This output provides one of the two input signals to the AND part of the FPHXORA, the other input is obtained from the FPHMSLC. Since when the EN2J1 is at logic low so is the Q1J1, then the AND gate is enabled and the output of the FPHXORA begins to generate the clock waveform. However, only one pulse is allowed to pass through the AND; when the first output pulse of the FPHXORA writes logic high to the FPHMSLC, one of the inputs of the AND is asserted low, effectively blocking further pulses from reaching the FPHMSLC. The EN2J1 is then asserted logic high, resulting in the transparent mode of the FPHDLAT.

To freeze the clock phases, the asynchronous EN3J1 signal must be asserted logic low. The EN2J1 is then asserted logic low and the FPHDLAT goes into the hold-mode; it maintains the last read data. In this mode, there is no transistions in the clock provided to the FPHFOUR and thus no new clock phases are generated. As long as the EN3J1 is asserted logic low, the EN2J1 remains asserted logic low and the clock also remains in the frozen state. During this period the activities of the FPHXORA are effectively ignored. When the EN3J1 is no longer asserted low, the events described in previous paragraphs occur.


4.2. SYNC and RESET Generator Circuit

The SYNC and RESET signals, as described in the Chapter 2, are used to communicate with the rest of the chips on the MCM. The SYNC is used to reset the phase generator circuits in those chips to the known states so that the clock phases at each of the chips on an MCM are synchronized. The RESET signals the instruction decoder that the clock has been deskewed and the permission has been granted for it to proceed with its normal operations.

The timing diagram specification for the SYNC/RESET (S/R) generator circuit is shown in Fig. 4.9. The SYNC is asserted logic low a half period (250 ps) after the LOCK is asserted logic high. This delay provides sufficient time margin to stop the master clock before the assertion of the SYNC. The master clock must remain logic high when it is stopped to ensure that the first clock phases are asserted logic high upon the receipt of the SYNC. This turns on Q1_69 of Fig. 4.3, which can provide current to either the PHCKT1 or the PHCKT3. As explained in the previous section, PHOUT1 is asserted logic high as long as the SYNC is also asserted logic high.

The master clock is stopped for at least 1.5 ns. The exact stopping time can be shorter depending on the length of the SYNC distribution. However, this time must be sufficiently large to allow for the propagation of the SYNC to all the chips on the MCM. Once the master clock is restarted, the S/R generator circuit counts up until 8 ns has passed and asserts the RESET for another 8 ns.

Fig. 4.10 shows the S/R generator circuit in a simplified form with just the single-ended wirings for clarity. Fig. 4.11 shows the differential version of the circuit with the minor details. This circuit can be divided into two parts that generate the SYNC and the RESET signals. The part that generates the SYNC is made up of the edge sensitive D-Latches that are sequentially asserted logic high (Fig. 4.9). One function of this circuit is to time the freeze duration of the master clock. The B3 is asserted logic high 1.5 ns after the assertion of B0. The XOR output, X, is then asserted logic high setting up for the transition of the FREEZE on the next master clock edge.

After the FREEZE is asserted logic high the master clock is restarted and the FRELAT is asserted logic low. Then, the clear inputs of the counter bits are asserted logic low allowing the counter to start. The RESET is asserted logic high when the counter has counted 1000002 and remains high until it has counted 1111112. On the next clock the RESET is asserted logic low. The duration of the RESET is specified to be between 2 ns to 8 ns. This specification is determined by the Boundary-Scan Test circuit used in the instruction decoder chip, which has been designed by Robert Philhower of the F-RISC/G group. The S/R generator circuit, as presented here, is designed to have the duration of 4 ns for the 2 GHz master clock. The RESLAT is asserted logic high after the detection of the falling edge of the RESET. Then, the clear input of the counter is asserted logic high and it is effectively stopped.

The level one to level two buffers are needed in a ripple counter, since each latch representing a bit is to be connected to two inputs of different levels; this exemplifies the drawback of the CML circuits in that the input levels can be different and must be matched when the connections are made between gates.

The SPICE simulation result, which is in accordance with the design specifications of Fig. 4.9, is shown in Fig. 4.12. This simulation shows five waveforms, they are from the top to bottom: the master clock waveform showing the clock stopping period; the LOCK waveform driven by the lock sense circuit; the FREEZE waveform with the logic low corresponding to the pause in the master clock; the SYNC waveform being asserted logic low after the pause in the master clock; and the RESET being asserted logic high about 4 ns after the restart of the master clock for the duration of 4 ns.


Fig. 4.9. The timing specification of the SYNC/RESET Generator circuit


Fig. 4.10. Simplified overview of the S/R generator circuit


Fig. 4.11a. The SYNC signal generator circuit (differential wiring)


Fig. 4.11b. The RESET signal generator circuit (differential wiring)

Fig. 4.12. The SPICE simulation of the S/R generator circuit