Chapter 5

Test Vehicle and TEST Plan

A test vehicle for the deskew scheme described in Chapter 2 has been designed. It is designed to deskew two clock signals, and is sufficient for the testing of the concept of the deskew scheme presented in this thesis. Fig. 5.1 highlights the block diagram of circuits introduced for testing; Fig. 5.2 shows rest of the block diagram including the PLL circuit.

The test vehicle was designed so that the testing of the clock skew between the different clock distribution paths is permitted on a wafer or chip without requiring the actual distribution on an MCM. This is achieved with the use of the VCDEs, labelled as the "delay" unit in Fig. 5.1. One set of the VCDEs has a fixed delay while the other set has been set up to vary with the external control signal. This control allows the determination of the maximum tolerable initial skew range. The testing strategy would be, to match the delay in the variable delay set of the VCDEs to the other set, then vary the delay in the VCDEs until the clock is no longer deskewed.

Balanced delay Exclusive-ORs (XORs) are used to determine the proper deskew condition. Each of the two inputs of the XORs are connected to the matching locations of different clock loops as shown in Fig. 5.1. One of the two XORs is placed to detect the deskew of the master clock (Clock Test) while the other is set up to detect the deskew of the first clock phase (Phase Test). The second XOR permits testing of the four clock phase generator circuit used in many F-RISC chips. Two four clock phase generator circuits are needed to determine the skew in the first clock phases. Provisions have been made so that the fourth clock phases are also available for observation. A well known characteristic of the XOR is that its output is asserted logic low whenever the two inputs match and logic high whenever the inputs do not. Hence, the XOR outputs at the Clock Test and the Phase Test pads are logic high until when the master clock and the clock phases are deskewed, at which point, the outputs are asserted logic low. In essence, the indirect objective of the test is to realize the logic low at the Clock Test and the Phase Test pads.

The Phase Generator Enable input to the phase generator circuits is designed to be supplied externally from the test chip. In the actual implementation of the phase generator circuit, this signal would be supplied from the boundary scan logic of the chip in consideration. Multiplexers are added to allow for the possibility of an actual usage of the test chip in the deskew of two clock signals after a successful test result. The multiplexer select control, Delay Select, would be set so that during the test mode, the clock loops are formed through the VCDEs mimicing the delay paths of an MCM clock distribution, and during the usage-mode, the clock loops would be formed through the differential drivers and receivers along with the actual clock distribution.

Fig. 5.1. Block diagram of additional circuits for the testing purpose

 

Fig. 5.2. Block diagram of rest of the test vehicle circuits

Table 5.1. Probe sites

Site 1

Site 2

Site 3

Clock Test

Clock Phase 1 A

Clock Freeze

Loop 0 Clock

Clock Phase 1 B

LOCK

VCDE Delay Control

Clock Phase 4 A

RESET

Delay Select

Clock Phase 4 B

DOWN

VCO Control

Phase Gen. Enable

UP

INIF

Phase Test

Filter Output

 

Table 5.2. Test vehicle parameters

Parameter

Value

Power Dissipation

1.85 W

Transistor Count

1030

Chip Size

2.6 mm x 3.0 mm

Fig. 5.3. The CASCADE probe pinouts

 

The Table 5.1 shows the probe sites of the deskew test chip shown in Fig. 5.3. There are three distinct types of pins shown in Table 5.1; test output signal pins, diagnosis signal pins, and control signal pins. While some of the pins, such as the Phase Test and Clock Test, are designed to signal the proper deskew of the master clock, pins such as the Filter Out, DOWN, and UP are designed to diagnose the possible causes of faults if the test chip fails. The signal pins, such as the VCDE Delay Control Select and VCO Control, comprise the third type of pins in that they are used to control the parameters of the test chip to yield information about the performance ranges of the deskew chip. The information such as the maximum master clock frequency and maximum tolerable delay difference in the clock loops can be obtained since the test chip is expected to fail under the extreme conditions. The summary descriptions of each of the signals pins are shown in the following list:

Test Output Signals

· Phase Test: Indicates the deskewed state of the clock phases.

· Clock Test: Indicates the deskewed state of the clocks.

· Clock Phase 1A: Observes the first clock phase from the first Phase Generator (A).

· Clock Phase 1B: Observes the second clock phase from the second Phase Generator (B).

· Clock Phase 4A: Observes the fourth clock phase from the Phase Generator A.

· Clock Phase 4B: Observes the fourth clock phase from the Phase Generator B.

· LOCK: Observes the LOCK signal from the lock senser.

Diagnosis Signals

· Clock Freeze: Observes the master clock freeze signal.

· RESET: Observes the RESET signal from the S/R generator to the instruction decoder.

· UP: Observes the UP signal generated in the phase detector.

· DOWN: Observes the DOWN signal generated in the phase detector.

· Filter Output: Observes the output of the filter.

Control Signals

· VCDE Delay Control: Controls the delay of the internal delay set.

· Delay Select: Selects between the internal and external delays.

· VCO Control: Controls the frequency of the VCO.

· INIF: Initializes the test chip.

· Phase Generator Enable: Enables the generation of the clock phases by the phase generator.

Since two CASCADE signal probes are available for the F-RISC/G team, only two of the probe sites can be used at any given time. A CASCADE signal probe has ten pins total, six signal pins and four power and ground pins as shown in Fig. 5.3. The signals of the probe sites have been selected to be compatible with the two probe testing limitation. In the Fig. 5.4, which contains the layout of the deskew chip, there is another probe site, the Probe Site 4. This site is not included in Table 5.1 because it is not used during the test-mode. This site contains the differential driver and receiver ports of the two clock loops for connections during the usage-mode. The floor plan and the pin outs of the deskew test chip are given in Fig. 5.5 and Fig. 5.6, respectively. Test vehicle parameters of the deskew chip are contained in Table 5.2.

Following is the test procedure for the deskew test chip:

1. Touch down on the probe sites 1 and 2.

1.1. Apply INIF to initialize the test chip.

1.2. Set Phase Generator Enable.

1.3. Set Delay Select to internal delay.

1.4. Set VCO Control to 2 GHz (observe Loop 0 Clock).

1.4.1. Set VCDE Delay Control to the minimum delay.

1.4.1.1. Observe Phase Test, Clock Test, LOCK and Clock Phases.

1.4.1.2. Switch on and off Phase Generator Enable to test the phase

generator.

1.4.1.3. Repeat Step 1.4.1 with new VCDE Delay Control setting until

1.4.1.1 shows failure.

1.4.1.4. Record current VCDE Delay Control voltage setting.

1.4.1.5. Measure initial skew (measure delay differences between the two first

clock phases after applying INIF).

1.4.2. Repeat Step 1.4 with new VCO Control voltage.

2. Touch down on the probe sites 1 and 3.

2.1. Apply INIF to initialize the test chip.

2.2. Observe Clock Freeze, RESET, UP, DOWN, and Filter Output signals to

diagnose any problems.

The expected test waveforms at the pins of some of the probe sites are shown in Fig. 5.7. The waveforms shows the qualitative behaviour; the time axis is not to scale and varies from waveform to waveform. During the actual test, the waveforms, UP and DOWN, could appear to be reversed depending on the state of the delay differences in the two clock loops.

 

 

Fig. 5.4. Layout of the deskew chip

 

Fig. 5.5. The floor plan of the deskew test chip

Fig. 5.6. I/O Pad layouts

 

Fig. 5.7. Expected test waveforms