As clock speeds of state of the art digital systems approach the Giga Hertz (GHz) range, one of the important issues that must be addressed for a synchronous digital system is the skew of the system clock.

A clock deskew scheme for a multi-GHz clock signal distributed on a Multi-Chip Module (MCM) is presented in this thesis. In this scheme, clock signals are distributed to various locations where the different distribution lengths channels are continuously monitored and deskewed by Phase-Locked Loop (PLL) circuits. The scheme promises to deskew clock signals to an arbitrarily small clock skew. The final skew in a practical implementation is determined by the performance of the PLLs and the delay mismatches of the drivers and receivers. The scheme is also applicable to a system clock with four phases. The circuits implementing the deskew scheme and the four-phase generator are described. A test chip has been designed and described along with the test plan. SPICE simulation indicates the final skew of 2 GHz clock signals to be within 5 ps.

The second part of this thesis describes a simple register file design that is well suited for achieving the speed potential of a fast but yield limited technology such as GaAs/AlGaAs heterojunction bipolar technology. A test chip for the register file has been fabricated and the test results indicate an access time of at least 500 ps.