Chapter 7


A clock deskew scheme for multi-GHz clock signals distributed on an MCM has been presented in this thesis. The scheme utilizes PLL circuits to continuously deskew clock signals. It promises to deskew clock signals to an arbitrarily small clock skew. The final skew in a practical implementation is determined by the performance of the PLLs and the delay mismatches of the drivers and receivers.

Presented in the thesis are the circuits of an implementation of the scheme. The SPICE simulation of the design suggests the final skew of less than 5 ps for a 2 GHz clock. A strategy has been outlined for extending the application of the scheme to a clock signal with multiple phases; the F-RISC processor, for which the deskew scheme has been developed, requires four clock phases. Thus, the circuits for a differential four phase generator with a "freeze" capability has been developed and presented. The four clock phases are generated from the rising and falling edges of the clock signal.

A simple register file design suitable for achieving the speed potential of a fast but yield limited technology has been presented. The simplicity of the design was instrumental in getting working circuits for a fast but still experimental process. It is also a significant factor in keeping the power dissipation level of the chip as low as possible.

A simple embedded test circuitry in accordance with the design philosophy of the register file has been developed to determine the access time. The test circuitry consists of two simple LFSRs and Exclusive-OR gates. Individual LFSRs were found to operate at clock speed of up to 2.5 GHz.

The test results indicate a 500 ps access time for the register file memory. A new register file has been designed with the improved estimation of the parasitic capacitances. SPICE simulation indicates an access time of less than 200 ps.