List of Tables

Table 3.1. The design parameters 40

Table 5.1. Probe sites 95

Table 5.2. Test vehicle parameters 95

Table 6.1. Number of transistors in the Test Chip 125

Table B.1. Parameters of the new register file design 135

Table B.2. Subcircuit currents of the register file 137

Table B.3. Parasitic Capacitances extracted with QUICKCAP 138

 

List of Figures

Fig. 1.1. General model of a digital system 4

Fig. 1.2. Propagation delay present in an inverter 7

Fig. 1.3. Example of a hazard 8

Fig. 1.4. Deskew scheme with chain of delay gates (Fouts) 10

Fig. 1.5. Deskew scheme with manual adjustment (Greub) 11

Fig. 1.6. Deskew scheme with PLLs (Johnson) 12

Fig. 2.1. Deskew scheme with internal reference delay (first scheme) 16

Fig. 2.2. Deskew scheme without internal reference delay (second scheme) 17

Fig. 2.3. Delay diagram for the first scheme 18

Fig. 2.4. Delay diagram for the second scheme 19

Fig. 3.1. Block diagram of the PLL 35

Fig. 3.2. Simple differential integrator filter circuit 40

Fig. 3.3. VCDE circuit 41

Fig. 3.4. Delay vs. Control Voltage 42

Fig. 3.5a. Ideal Digital Phase Detector characteristics 44

Fig. 3.5b.Actual Digital Phase Detector characteristics 44

Fig. 3.6a. Expected UP and DOWN signals as the PLLs are locked 45

Fig. 3.6b. SPICE simulation of UP and DOWN signals 45

Fig. 3.7. Two potential lock states for phase detector 50

Fig. 3.8. Phase Detector circuit 51

Fig. 3.9. RS3 circuit 52

Fig. 3.10. PD1MSLC circuit 53

Fig. 3.11. OR1 of Phase Detector circuit 54

Fig. 3.12. Schmitt Trigger (Level 3) 55

Fig. 3.13. Gate Keeper (GATEKPR) 56

Fig. 3.14. Amplifier circuit 59

Fig. 3.15. Amplifier frequency and phase response plots 60

Fig. 3.16. Filter frequency and phase response plots 61

Fig. 3.17a. Driver circuit 62

Fig. 3.17b. Receiver circuit 62

Fig. 3.18a. LOCK generation timing diagram 64

Fig. 3.18b. SPICE simulation of LOCK generation 64

Fig. 3.19. Lock sensor 65

Fig. 3.20. Overview of the deskewing process 66

Fig. 3.21. Inital skew of 110 ps 67

Fig. 3.22. Final skew 68

Fig. 3.23. The filter output behaviour in response to the activation of the limiting circuit 69

Fig. 4.1. The SPICE simulation of the Clock Phase Generator circuit with the FREEZE signal asserted 72

Fig. 4.2. The toplevel view of the Clock Phase Generator circuit 74

Fig. 4.3. The toplevel view of the Four Phase Generator circuit (FPHFOUR) 75

Fig. 4.4. The first clock phase generator circuit 76

Fig. 4.5. The second, third, and fourth clock phases generator circuit 77

Fig. 4.6. A simple D-Latch circuit in CML logic (FPHDLAT) 79

Fig. 4.7. A simple master-slave latch in CML logic (FPHMSLC) 80

Fig. 4.8. A circuit that combines AND and Exclusive-OR functions 81

Fig. 4.9. The timing specification of the SYNC/RESET Generator circuit 86

Fig. 4.10. Simplified overview of the S/R generator circuit 87

Fig. 4.11a. The SYNC signal generator circuit (differential wiring) 88

Fig. 4.11b. The RESET signal generator circuit (differential wiring) 89

Fig. 4.12. The SPICE simulation of the S/R generator circuit 90

Fig. 5.1. Block diagram of additional circuits for the testing purpose 93

Fig. 5.2. Block diagram of rest of the test vehicle circuits 94

Fig. 5.3. The CASCADE probe pinouts 96

Fig. 5.4. Layout of the deskew chip 101

Fig. 5.5. The floor plan of the deskew test chip 102

Fig. 5.6. I/O Pad layouts 103

Fig. 5.7. Expected test waveforms 104

Fig. 6.1. Overall Register File circuit 108

Fig. 6.2. Address Driver circuit 109

Fig. 6.3. Word Line voltage swing 110

Fig. 6.4. Write operation and critical internal Threshold Voltage signals 112

Fig. 6.5. Threshold Generator circuit 114

Fig. 6.6. Block diagram of the Register File test scheme 118

Fig. 6.7. Timing diagram for performance test 119

Fig. 6.8. Photograph of fabricated test chip 121

Fig. 6.9. VCO Output, 50 mV/div 200 ps/div 122

Fig. 6.10. LFSR output operating at 1 GHz, 50mV/div 123

Fig. 6.11. Register File output with one error, 50 mV/div 123

Fig. 6.12. Forced output errors, 50 mV/div 124

Fig. 6.13. LFSR output operating at 2.5 GHZ, 50 mV/div 124

Fig. B.1. SPICE simulation result of the new register file design 138

Fig. B.2. Memory hold voltage is greater than 250 mV 139

Fig. B.3. Write pulse rises above the selected memory cells by greater than 80 mV 140

Fig. B.4. Read/Write Threshold voltage at 50%-60% of the selected memory cell 141

Fig. B.5. Word Line swing is greater than 800mV in magnitude 142

Fig. B.6. OPAMP output voltages are less than 50 mV 143

Fig. B.7. Layout of the memory cell 144

Fig. B.8. Overall Register File layout 145

Fig. D.1. XOR outputs for different clock skews 147

Fig. D.2. Filter output response during the lock state to the varying internal VCDE delays 148

Fig. D.3. Final clock skew at the internal VCDE delays 149