To my parents

Contents

List of Tables vi

List of Figures vii

Acknowledgments xi

Abstract xii

Chapter 1. Introduction and Historical Review 1

1.1. Skew 3

1.2. Hazard 5

1.3. Survey of Existing Clock Deskew Methods 9

Chapter 2. Clock Deskew Scheme 14

2.1. Deskew Schemes 20

2.1.1. Restrictions Placed on the Scheme 22

2.1.2. Synchronization Procedure for a Clock with Multiple Phases 24

2.1.3. The Final Clock Skew Error for the First Deskew Scheme 25

2.1.4. The Overall Clock Skew Error for the Second Deskew Scheme 29

2.1.6. Notational Definitions 33

Chapter 3. Circuits for the Deskew Scheme 35

3.1. Analysis of the CLOCK Loops 36

3.2. PLL Design 42

3.2.1. VCDE 42

3.2.2. Phase Detector 46

3.2.3. Filter 58

3.2.4. Drivers and Receivers 64

3.2.5. Lock condition sensor 64

3.3. Overall circuit simulation results 71

Chapter 4. Four Clock Phase and SYNC/RESET Generator Circuits 71

4.1. Clock Phase Generator Circuit 71

4.2. SYNC and RESET Generator Circuit 83

Chapter 5. Test Vehicle and TEST Plan 91

Chapter 6. A 500 ps 32 8 bit Register File Implemented in GaAs/AlGaAs HBTs 105

6.1. Circuit Description 106

6.1.1. Address Line Driver 106

6.1.2. Memory Cell 109

6.1.3. Write Circuit 111

6.1.4. Threshold Voltage Generator 113

6.1.5. Key Interconnect Parasitic Capacitances 115

6.2. Test Scheme 115

6.2.1. Testing Methodology 116

6.2.2. Detecting BIST Failures 119

6.2.3. Final Design 120

6.3. Test Results 121

6.3.1. BIST Support Circuitry 122

6.3.2. Register File Memory 127

Chapter 7. Conclusions 126

Literature Cited 128

Appendix A. Differential Integrator with Finite Gain Amplifier 131

Appendix B. A New Register File Design 134

Appendix C. To Change Phase Detector State 146

Appendix D. Key Test Signals 147