Current Research Focus: Data storage and memory system design across software and hardware stacks

We always look for well-motivated students to join our group. Because of the inter-disciplinary nature and practical importance of our research, students will have excellent opportunities to pursue creative and rewarding research. This will put our students in very good positions for their future careers. Many our former group members are now holding senior technical/management positions at leading-edge high-tech companies and even founded their own startup companies. If you wonder why we focus on data storage and memory, consider the follows:

  1. World-wide data volumes reached 1.2 zettabytes in 2010 and are expected to grow 44 fold over the course of this decade;
  2. It has been predicted that solid-state storage has the potential to become a $100 billion/year market by the close of this decade;
  3. The information industry is experiencing exciting data-centric paradigm shifts, e.g., data-intensive computing, in-memory computing, and cloud storage, to name a few.

We gratefully acknowledge the support from the following funding agencies and companies.

           


               

         

           

Related Conferences

My Google Scholar Publication Page

Journal Papers:

  1. X. Zhang, D. Xiong, K. Zhao, C. W. Chen, and T. Zhang, Realizing Low-Cost Flash Memory Based Video Caching in Content Delivery Systems, IEEE Transactions on Circuits and Systems for Video Technology, accepted
  2. F. Chen, T. Zhang, and X. Zhang, Software Support Inside and Outside Solid-State Devices for High Performance and High Efficiency, Proceedings of the IEEE, vol. 105, issue 9, pp. 1650-1665, Sept. 2017
  3. X. Zhang, J. Li, H. Wang, D. Xiong, J. Qu, H. Shin, J. P. Kim, and T. Zhang, Realizing Transparent OS/Apps Compression in Mobile Devices at Zero Latency Overhead, IEEE Transactions on Computers, vol. 66, issue 7, pp. 1188-1199, July 2017
  4. H. Wang, K. Zhao, M. Lv, X. Zhang, H. Sun, and T. Zhang, Improving 3D DRAM Fault Tolerance through Weak Cell Aware Error Correction, IEEE Transactions on Computers, vol. 66, issue 5, pp. 820-833, May 2017
  5. H. Sun, W. Zhao, M. Lv, G. Dong, N. Zheng, and T. Zhang, Exploiting Intra-cell Bit Error Characteristics to Improve Min-sum LDPC Decoding for MLC NAND Flash based Storage in Mobile Device, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, issue 8, pp. 2654-2664, Aug. 2016
  6. N. Zheng, J. Li, S. Dahandeh, and T. Zhang, Self-directed Equalization for Magnetic Recording Channels with Multi-sensor Read Head, IEEE Transactions on Magnetics, vol. 52, issue 1, pp. 1-6, Jan. 2016
  7. J. Yang, B. Geller, M. Li, and T. Zhang, An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, issue 3, pp. 979-991, March 2016
  8. H. Wang, K. Zhao, J. Li, and T. Zhang, Optimizing the Use of STT-RAM in SSDs through Data-Dependent Error Tolerance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, issue 11, pp. 2743-1747, Nov. 2015
  9. J. Li, K. Zhao, J. Ma, and T. Zhang, True-Damage-Aware Enumerative Coding for Improving NAND Flash Memory Endurance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, issue 6, pp. 1165-1169, June 2015
  10. N. Zheng and T. Zhang, Design of Low-Complexity 2-D SOVA Detector for Shingled Magnetic Recording, IEEE Transactions on Magnetics, vol. 51, issue 4, April 2015
  11. K. Zhao, J. Li, J. Ma, R. Micheloni, and T. Zhang, Overclocking NAND Flash Memory IO Link in LDPC-based SSDs, IEEE Transactions on Circuits and Systems II, vol. 61, issue 11, pp. 885-889, Nov. 2014
  12. Q. Wu, K. Venkataraman, and T. Zhang, OFWAR: Reducing SSD Response Time Using On-demand Fast-Write-and-Rewrite, IEEE Transactions on Computers, vol. 63, issue 10, pp. 2500-2512, Oct. 2014 (PDF)
  13. J. Li, K. Zhao, J. Ma, and T. Zhang, Realizing Unequal Error Correction for NAND Flash Memory at Minimal Read Latency Overhead, IEEE Transactions on Circuits and Systems II, vol. 61, no. 5, pp. 354-358, May 2014 (PDF)
  14. N. Zheng, K. Venkataramany, A. Kavcic, and T. Zhang, A Study of Multi-track Joint 2D Signal Detection Performance and Implementation Cost for Shingled Magnetic Recording, IEEE Transactions on Magnetics, vol. 50, issue 6, pp. 1-6, June 2014 (PDF)
  15. G. Dong, Y. Pan, and T. Zhang, Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, issue 6, pp. 1270-1280, June 2014 (PDF)
  16. J. Wang, K. Vakilinia, T.-Y. Chen, T. Courtade, G. Dong, T. Zhang, H. Shankar, and R. Wesel, Enhanced Precision Through Multiple Reads for LDPC Decoding in Flash Memories, IEEE Journal on Selected Areas in Communications, vol. 32, issue 5, pp. 880-891, May 2014 (PDF)
  17. G. Wu, X. He, N. Xie, and T. Zhang, Exploiting Workload Dynamics to Improve SSD Read Latency via Differentiated Error Correction Codes, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 18, issue 4, Oct. 2013
  18. X. Huang, A. Kavcic, X. Ma, G. Dong, T. Zhang, Multilevel Flash Memories: Channel Modeling, Capacities and Optimal Coding Rates, International Journal on Advances in Systems and Measurements, vol. 6, pp. 364-373, 2013
  19. K. Venkataraman, G. Dong, N. Xie, and T. Zhang, Reducing Read Latency of Shingled Magnetic Recording with Severe Inter-Track Interference using Transparent Lossless Data Compression, IEEE Transactions on Magnetics, vol. 49, issue 8, pp. 4761-4767, 2013 (PDF)
  20. G. Dong, N. Xie, and T. Zhang, Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead, IEEE Transactions on Circuits and Systems I, vol. 60, issue 9, pp. 2412-2421, 2013 (PDF)
  21. K. Venkataraman, Y. Li, Q. Wu, N. Xie, H. Sun, N. Zheng, and T. Zhang, Using Planar Embedded DRAM in Memory Intensive Signal Processing Circuits: Case Studies on LDPC Decoding and Motion Estimation, Journal of Signal Processing Systems, vol. 73, issue 1, pp. 11-24, 2013
  22. Q. Wu, F. Sun, W. Xu, and T. Zhang, Using Multi-Level Phase Change Memory to Build Data Storage: A Time-Aware System Design Perspective, IEEE Transactions on Computers, vol. 62, issue 10, pp. 2083-2095, 2013 (PDF)
  23. Y. Pan, G. Dong, and T. Zhang, Error Rate Based Wear-Leveling for NAND Flash Memory at Highly Scaled Technology Nodes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, issue 7, pp. 1350-1354, 2013 (PDF)
  24. Y. Pan, G. Dong, N. Xie, and T. Zhang, On the Case of Using Quasi-EZ-NAND Flash Memory to Build Future Solid-State Drives, IEEE Transactions on Computers, vol. 62, no. 5, pp. 1051-1057, 2013 (PDF)
  25. Y. Pan, Y. Li, H. Sun, W. Xu, N. Zheng, and T. Zhang, Exploring the Use of Emerging Non-volatile Memory Technologies in Future FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, issue 4, pp. 771-775, 2013 (PDF)
  26. H. Sun, C. Liu, T. Min, N. Zheng, and T. Zhang, Architectural Exploration to Enable Sufficient MTJ Device Write Margin for MRAM-based Cache, IEEE Transactions on Magnetics, vol. 48, issue 8, pp. 2346-2351, 2012 (PDF)
  27. G. Dong, Y. Pan, N. Xie, C. Varanasi, and T. Zhang, Estimating Information-Theoretical NAND Flash Memory Storage Capacity and Its Implication to Memory System Design Space Exploration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, issue 9, pp. 1705-1714, 2012 (PDF)
  28. Y. Li, G. Dong, and T. Zhang, Joint Source-Channel Coding and Channelization for Embedded Video Processing with Flash Memory Storage, IEEE Transactions on Signal Processing, vol. 60, issue 8, pp. 4403-4414, 2012 (PDF)
  29. K. Venkataraman, G. Dong, and T. Zhang, Techniques Mitigating Update-Induced Latency Overhead in Shingled Magnetic Recording, IEEE Transactions on Magnetics, vol. 48, issue 5, pp. 1899-1905, 2012 (PDF)
  30. Y. Li and T. Zhang, Reducing DRAM Image Data Access Energy Consumption in Video Processing, IEEE Transactions on Multimedia, vol. 14, issue 2, pp. 303-313, 2012 (PDF)
  31. Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang, A 130nm 1.2V/3.3V 16Kb Spin-Transfer Torque Random Access Memory with Nondestructive Self-Reference Sensing Scheme, IEEE Journal of Solid State Circuits (JSSC), vol. 47, issue 2, pp. 560-573, 2012 (PDF)
  32. H. Sun, C. Liu, W. Xu, N. Zheng, and T. Zhang, Using Magnetic RAM to Build the Low Power and Soft Error Resilient L1 Cache, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, issue 1, pp. 19-28, 2012 (PDF)
  33. Q. Wu and T. Zhang, Design Techniques to Facilitate Processor Power Delivery in 3D Processor-DRAM Integrated Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, issue 9, pp. 1655-1666, 2011 (PDF)
  34. W. Xu and T. Zhang, A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multi-Level Phase-Change Memory in the Presence of Significant Resistance Drift, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, issue 8, pp. 1357-1367, 2011 (PDF)
  35. H. Sun, P. Ren, N. Zheng, T. Zhang, and T. Li, Architecting High-Performance Energy-Efficient Soft Error Resilient Cache under 3D Integration Technology, Microprocessors and Microsystems, vol. 35, issue 4, pp. 371-381, 2011
  36. W. Xu, H. Sun, X. Wang, Y. Chen, and T. Zhang, Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, issue 3, pp. 483-493, 2011 (PDF)
  37. N. Xie, G. Dong, and T. Zhang, Using Lossless Data Compression in Data Storage Systems: Not For Saving Space, IEEE Transactions on Computers, vol. 60, issue 3, pp. 335-345, 2011 (PDF)
  38. G. Dong, N. Xie, and T. Zhang, On the Use of Soft-Decision Error Correction Codes in NAND Flash Memory, IEEE Transactions on Circuits and Systems I, vol. 58, issue 2, pp. 429-439, 2011 (PDF)
  39. G. Dong, S. Li, and T. Zhang, Using Data Post-compensation and Pre-distortion to Tolerate Cell-to-Cell Interference in MLC NAND Flash Memory, IEEE Transactions on Circuits and Systems I, vol. 57, issue 10, pp. 2718-2728, 2010 (PDF)
  40. S. Li and T. Zhang, Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, issue 10, pp. 1412-1420, 2010 (PDF)
  41. L. Liu, F. Ye, X. Ma, T. Zhang, and J. Ren, A 1.1 Gb/s 115 pJ/bit Configurable MIMO Detector using 0.13um CMOS Technology, IEEE Transactions on Circuits and Systems II, vol. 57, no. 9, pp. 701-705, 2010 (PDF)
  42. Y. Li, Y. Liu, and T. Zhang, Exploiting Three-Dimensional (3D) Memory Stacking to Improve Image Data Access Efficiency for Motion Estimation Accelerators, Elsevier Journal on Signal Processing: Image Communication (Special issue on Breakthrough Architectures for Image and Video Systems), vol. 25, issue 5, 2010 (PDF)
  43. Y. Liu, T. Zhang, and K. K. Parhi, Computation Error Analysis in Digital Signal Processing Systems with Overscaled Supply Voltage, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, issue 4, pp. 517-526, 2010 (PDF)
  44. N. Xie, T. Zhang, and E. F. Haratsch, Improving Burst Error Tolerance of LDPC-Centric Coding Systems in Read Channel, IEEE Transactions on Magnetics, vol. 46, no. 3, pp. 933-941, 2010 (PDF)
  45. J. Lee, J. Moon, T. Zhang, and E. Haratsch, New Phase-Locked Loop Design: Understanding the Impact of a Phase-Tracking Channel Detector, IEEE Transactions on Magnetics, vol. 46, no. 3, pp. 830-836, 2010 (PDF)
  46. N. Xie, T. Zhang, and E. F. Haratsch, Using Embedded DRAM to Reduce Energy Consumption of Magnetic Recording Read Channel, IEEE Transactions on Magnetics, vol. 46, no. 1, pp. 87-91, 2010 (PDF)
  47. W. Xu, T. Zhang, and Y. Chen, Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, issue 1, pp. 66-74, 2010 (PDF)
  48. H. Sun, J. Liu, R. Anigund, N. Zheng, J.-Q. Lu, K. Rose, and T. Zhang, Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems, IEEE Design & Test, vol. 26, issue 5, pp. 36-47, Oct. 2009 (PDF)
  49. H. Sun, N. Zheng, and T. Zhang, Leveraging Access Locality for the Efficient Use of Multi-bit Error Correcting Codes in L2 Cache, IEEE Transactions on Computers, vol. 58, issue 10, pp. 1297-1306, Oct. 2009 (PDF)
  50. Y. Liu, T. Zhang, and J. Hu, Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, issue 3, pp.439-443, March 2009 (PDF)
  51. T. Zhang, R. Micheloni, J.-Q. Lu, and Z. R. Huang, 3D Storage, Power Delivery and RF/Optical Transceiver - Case Studies of 3D Integration from System Design Perspectives, Proceedings of the IEEE (special issue on 3D Integration Technology), invited, vol. 97, issue 1, pp.161-174, Jan. 2009 (PDF)
  52. N. Xie, W. Xu, T. Zhang, E. F. Haratsch, and J. Moon, Concatenated LDPC and BCH Coding System for Magnetic Recording Read Channel with 4K-Byte Sector Format, IEEE Transactions on Magnetics, vol. 44, no. 12, pp. 4784-4789, Dec. 2008 (PDF)
  53. Y. Xin, A. Mujitaba, T. Zhang, and J. Jiang, Bypass Decoding -- A Reduced Complexity Decoding Technique for LDPC Coded MIMO-OFDM Systems, IEEE Transactions on Vehicular Technology, vol. 57, issue 4, pp. 2319-2333, July 2008 (PDF)
  54. S. Li and T. Zhang, Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits, Nanotechnology, 19 (2008) 185202
  55. F. Sun and T. Zhang, Use of Parity Checks Inherent in LDPC Codes for Dominant Error Events Detection and k-Constraint Enforcement, IEEE Transactions on Magnetics, vol. 43, issue 12, pp. 4113-4116, 2007 (PDF)
  56. H. Zhong, W. Xu, N. Xie, and T. Zhang, Area-Efficient Min-Sum Decoder Design for High-Rate QC-LDPC Codes in Magnetic Recording, IEEE Transactions on Magnetics, vol. 43, issue 12, pp. 4117-4122, 2007 (PDF)
  57. F. Sun and T. Zhang, Quasi-Reduced-State Soft-Output Viterbi Detector for Magnetic Recording Read Channel, IEEE Transactions on Magnetics, vol. 43, issue 10, pp. 3921-3924, 2007 (PDF)
  58. F. Sun, L. Feng, and T. Zhang, Run-Time Data-Dependent Defect Tolerance for Hybrid CMOS/Nanodevice Digital Memories, IEEE Transactions on Nanotechnology, vol. 6, issue 3, pp. 341-351, 2007 (PDF)
  59. F. Sun, S. Devarajan, K. Rose, and T. Zhang, Design of On-Chip Error Correction Systems for Multilevel NOR and NAND Flash Memories, IET Circuits, Devices & Systems, vol. 1, issue 3, pp. 241-249, June 2007 (PDF)
  60. F. Sun and T. Zhang, Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder, IEEE Transactions on Circuits and Systems I, vol. 54, no. 5, pp. 1060-1068, May 2007 (PDF)
  61. F. Sun and T. Zhang, Defect and Transient Fault Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories, IEEE Transactions on Nanotechnology, vol. 6, no. 3, pp. 341-351, May 2007 (PDF)
  62. S. Chen, T. Zhang, and Y. Xin, Relaxed K-best MIMO Signal Detector Design and VLSI Implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, issue 3, pp. 328-337, March 2007 (PDF)
  63. H. Zhong, T. Zhang, and E. F. Haratsch, Quasi-Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI Implementation, IEEE Transactions on Magnetics, vol. 43, issue 3, pp. 1118-1123, March 2007 (PDF)
  64. F. Sun and T. Zhang, Parallel High-Throughput Limited Search Trellis Decoder VLSI Design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, number 9, pp. 1013-1022, September 2005 (PDF)
  65. S. Chen and T. Zhang, Self-Timed Dynamically Pipelined Adaptive Signal Processing System: A Case Study of DLMS Equalizer for Read Channel, IEEE Transactions on Circuits and Systems I, vol. 52, issue 7, pp. 1338-1347, July 2005 (PDF)
  66. H. Zhong and T. Zhang, Block-LDPC: A practical LDPC coding system design approach, IEEE Transactions on Circuits and Systems I, vol. 52, issue 4, pp. 766-775, April 2005 (PDF)
  67. T. Zhang and K. K. Parhi, Joint (3,k)-Regular LDPC Code and Decoder/Encoder Design, IEEE Transactions on Signal Processingvol. 52, no. 4, pp. 1065-1079, April 2004 (PDF)(PS)
  68. T. Zhang and K. K. Parhi, An FPGA Implementation of (3,6)-Regular Low-Density Parity-Check Code Decoder, EURASIP Journal on Applied Signal Processing, special issue on Rapid Prototyping of DSP Systems vol. 2003, no. 6, pp. 530-542, May 2003 (PDF)(PS)
  69. T. Zhang and K. K. Parhi, Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials, IEEE Transactions on Computers, vol. 50, pp. 734-749, July 2001 (PDF)(PS)

Conference Papers:

  1. N. Zheng, M. Lyu, and T. Zhang, An Exploratory Study on Data Layout Configurable Shingled Recoding Hard Disk Drives, International Workshop of Software-Defined Data Communications and Storage (SDDCS) , April 2017
  2. Y. Li, H. Wang, X. Zhang, N. Zheng, S. Dahandeh, and T. Zhang, Facilitating Magnetic Recording Technology Scaling for Data Center Hard Disk Drives through Filesystem-level Transparent Local Erasure Coding, USENIX Conference on File and Storage Technologies (FAST), Feb. 2017
  3. Y. Li, H. Wang, X. Zhao, H. Sun, and T. Zhang, Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud, International Symposium on Memory Systems (MEMSYS), Oct. 2016
  4. H. Wang, Y. Li, X. Zhang, X. Zhao, H. Sun, and T. Zhang, On the Use of DRAM with Unrepaired Weak Cells in Computing Systems, International Symposium on Memory Systems (MEMSYS), Oct. 2016
  5. X. Zhang, J. Li, H. Wang, K. Zhao, and T. Zhang, Reducing Solid-State Storage Device Write Stress Through Opportunistic In-Place Delta Compression, USENIX Conference on File and Storage Technologies (FAST), Feb. 2016
  6. W. Li, G. Jean-Baptise, J. Riveros, G. Narasimhan, T. Zhang, and M. Zhao, CacheDedup: In-line Deduplication for Flash Caching, USENIX Conference on File and Storage Technologies (FAST), Feb. 2016
  7. X. Zhang, J. Li, K. Zhao, H. Wang, and T. Zhang, Leveraging Progressive Programmability of SLC Flash Pages to Realize Zero-overhead Delta Compression for Metadata Storage, USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage), July, 2015
  8. H. Wang, K. Zhao, and T. Zhang, Efficiently Realizing Weak Cell Aware DRAM Error Tolerance for Sub-20nm Technology Nodes, International Memory Workshop (IMW), May 2015
  9. J. Li, K. Zhao, X. Zhang, J. Ma, M. Zhao, and T. Zhang, How Much Can Data Compressibility Help to Improve NAND Flash Memory Lifetime?, USENIX Conference on File and Storage Technologies (FAST), Feb. 2015
  10. X. Zhang, Y. Li, J. Li, K. Zhao, and T. Zhang, Proximate Control Stream Assisted Video Transcoding for Heterogeneous Content Delivery Network, IEEE International Conference on Image Processing (ICIP), Oct. 2014
  11. W. Zhao, H. Sun, M. Lv, G. Dong, N. Zheng, and T. Zhang, Improving Min-sum LDPC Decoding Throughput by Exploiting Intra-cell Bit Error Characteristic in MLC NAND Flash Memory, IEEE Symposium on Massive Storage Systems and Technologies (MSST), June 2014
  12. H. Wang and T. Zhang, An Exploratory Study on System-aided DRAM Scaling, International Memory Workshop (IMW), May 2014
  13. K. Zhao, K. Venkataraman, X. Zhang, J. Li, N. Zheng, and T. Zhang, Over-Clocked SSD: Safely Running Beyond Flash Memory Chip I/O Clock Specs, IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2014
  14. K. Venkataraman, W. Zhao, H. Sun, N. Zheng, and T. Zhang, Scheduling Algorithms for Handling Updates in Shingled Magnetic Recording, IEEE International Conference on Networking, Architecture, and Storage (NAS), July 2013
  15. K. Zhao, W. Zhao, H. Sun, T. Zhang, X. Zhang, and N. Zheng, LDPC-in-SSD: Making Advanced Error Correction Codes Work Effectively in Solid State Drives, USENIX Conference on File and Storage Technologies (FAST), Feb. 2013
  16. G. Dong, Y. Zou, and T. Zhang, Reducing Data Transfer Latency of NAND Flash Memory with Soft-Decision Sensing, ICC Workshop on Emerging Data Storage Technologies, June 2012
  17. J. Wang, G. Dong, T. Zhang, and R. Wesel, Use Mutual-Information Optimized Quantization in LDPC decoding for Flash Memory, Annual Non-Volatile Memories Workshop, March 2012
  18. J. No, J. Moon, J. Yang, S. Joo, S. Lee, S. Choi, H. Lee, and T. Zhang, Characterizing Cell-to-Cell Coupling in Flash Memory, International Conference on Electronics, Information, and Communication (ICEIC), Feb. 2012
  19. Y. Pan, G. Dong, Q. Wu, and T. Zhang, Quasi-Nonvolatile SSD: Trading Flash Memory Nonvolatility to Improve Storage System Performance for Enterprise Applications, IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2012
  20. H. Sun, J. Zhao, F. Wang, N. Zheng, and T. Zhang, Cost-Efficient Built-In Repair Analysis for Embedded Memories with On-Chip ECC, International Symposium on Access Spaces (IEEE-ISAS), June 2011 (Best Paper Award)
  21. Q. Wu, G. Dong, and T. Zhang, Exploiting Heat-Accelerated Flash Memory Wear-Out Recovery to Enable Self-Healing SSDs, USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage) , June 2011
  22. H. Sun, C. Liu, N. Zheng, T. Min, and T. Zhang, Design Techniques to Improve the Device Write Margin for MRAM-based Cache Memory, ACM Great Lakes symposium on VLSI (GLSVLSI), May 2011
  23. Y. Pan, G. Dong, and T. Zhang, Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance, USENIX Conference on File and Storage Technologies (FAST), Feb. 2011
  24. G. Dong, N. Xie, and T. Zhang, Techniques for Embracing Intra-Cell Unbalanced Bit Error Characteristics in MLC NAND Flash Memory, Workshop on Application of Communication Theory to Emerging Memory Technologies (in conjection with IEEE Globecom), Dec. 2010
  25. H.-H. Wu, C.-C. Shen, S. S. Bhattacharyya, K. Compton, M. Schulte, M. Wolf, and T. Zhang, Design and Implementation of Real-time Signal Processing Applications on Heterogeneous Multiprocessor Arrays, Asilomar Conference on Signals, Systems, and Computers, Nov. 2010
  26. N. Xie, G. Dong and T. Zhang, Applying Transparent Lossless Data Compression to Facilitate the Use of Advanced Error Correction Codes in Solid-State Drives, IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2010
  27. G. Wu, X. He, N. Xie and T. Zhang, DiffECC: Improving SSD Read Performance Using Differentiated Error Correction Coding Schemes, IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), Aug. 2010 (Nominated for Best Paper Award)
  28. Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu and T. Zhang, Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2010 (Best Paper Award)
  29. W. Xu and T. Zhang, Using Time-Aware Memory Sensing to Address Resistance Drift Issue in Multi-Level Phase Change Memory, IEEE International Symposium on Quality Electronic Design (ISQED), March 2010
  30. Y. Liu, J. Liu, and T. Zhang, Design of Low-Power Variation Tolerant Signal Processing Systems with Adaptive Finite Word-length Configuration, IEEE International Symposium on Quality Electronic Design (ISQED), March 2010
  31. Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang, A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM), Design, Automation & Test in Europe Conference and Exhibition (DATE), March 2010
  32. Y. Pan and T. Zhang, DRAM-Based FPGA Enabled by Three-Dimensional (3D) Memory Stacking, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2010
  33. J. Lee, J. Moon, T. Zhang, and E. Haratsch, New PLL Design: Understanding the Impact of a Phase-Tracking Channel Detector, The Magnetic Recording Conference (TMRC), Oct. 2009
  34. Q. Wu, K. Rose, J.-Q. Lu, and T. Zhang, Impacts of Though-DRAM Power Vias in 3D Processor-DRAM Integrated Systems, IEEE 3D System Integration Conference, Sept. 2009
  35. A. Beece, K. Rose, T. Zhang, and J.-Q. Lu, Impact of Model Accuracy on 3D Design, IEEE 3D System Integration Conference, Sept. 2009
  36. Z. Xu, A. Beece, K. Rose, T. Zhang, and J.-Q. Lu, Modeling and Evaluation for Electrical Characteristics of Through Strata Vias (TSVs) in Three-Dimensional Integration, IEEE 3D System Integration Conference, Sept. 2009
  37. W. Xu, J. Liu, and T. Zhang, Data Manipulation Techniques to Reduce Phase Change Memory Write Energy, International Symposium on Low Power Electronics and Design (ISLPED), August 2009
  38. Y. Pan and T. Zhang, Improving VLIW Processor Performance using Three-Dimensional (3D) DRAM Stacking, IEEE Application-specific Systems, Architectures and Processors (ASAP), July 2009
  39. Q. Wu, K. Rose, J.-Q. Lu, and T. Zhang, On the Impact of Though-DRAM Power Vias in 3D Processor-DRAM Integrated Systems, SRC TECHCON, Sept. 2009
  40. S. Li and T. Zhang, Let CNT and Metal Cooperate other than Compete in Future Integrated Circuits, SRC TECHCON, Sept. 2009
  41. S. Li and T. Zhang, Using Carbon Nanotubes in Digital Memories, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), July 2009
  42. W. Xu, X. Wang, Y. Chen, and T. Zhang, Improving STT MRAM Storage Density through Smaller-Than-Worst-Case Transistor Sizing, Design Automation Conference (DAC), July 2009
  43. H. Li, H. Xi, Y. Chen, X. Wang, and T. Zhang, Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration, IEEE Computer Society Annual Symposium on VLSI, May 2009
  44. S. Li and T. Zhang, Approaching the Information Theoretical Bound of Multi-Level NAND Flash Memory Storage Efficiency, International Memory Workshop, May 2009
  45. Q. Wu, J.-Q. Lu, K. Rose, and T. Zhang, Efficient Implementation of Decoupling Capacitors in 3D Processor-DRAM Integrated Computing Systems, ACM Great Lakes Symposium on VLSI, May 2009
  46. S. Li and T. Zhang, Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated TCM-BCH Coding, ACM Great Lakes Symposium on VLSI, May 2009
  47. R. Anigundi, H. Sun, J. Lu, K. Rose, and T. Zhang, Architecture Design Exploration of Three-Dimensional (3D) Integrated DRAM, IEEE International Symposium on Quality Electronic Design (ISQED), March 2009
  48. S. Li and T. Zhang, Exploratory Study on Circuit and Architecture Design of Very High Density Diode-Switch Phase Change Memories, IEEE International Symposium on Quality Electronic Design (ISQED), March 2009
  49. H. Sun, J. Liu, N. Zheng, J.-Q. Lu, K. Rose, and T. Zhang, Multi-Core Computer Memory Hierarchy Design using Heterogeneous Three-Dimensional (3D) Stacked DRAM , Workshop of 3D integration and interconnect-centric architectures in conjunction with International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2009
  50. H. Sun, N. Zheng, and T. Zhang, Realization of L2 Cache Defect Tolerance Using Multi-bit ECC, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2008
  51. Y. Liu, T. Zhang, and K. K. Parhi, Analysis of Voltage Overscaled Computer Arithmetics in Low Power Signal Processing Systems, IEEE Asilomar Conference on Signals, Systems, and Computers, Oct. 2008
  52. H. Sun, N. Zheng, and T. Zhang, Algorithm and VLSI Architecture Design for Variable Block Size Motion Compensated De-interlacing, IEEE Asilomar Conference on Signals, Systems, and Computers, Oct. 2008
  53. S. Li and T. Zhang, Decoder and Sensing Circuit Design Approaches for High-Density Diode-Switch Phase Change RAM, SRC TECHCON, Sept. 2008
  54. W. Xu, T. Zhang and Y. Chen, Spin-Transfer Torque Magnetoresistive Content Addressable Memory (CAM) Cell Structure Design with Enhanced Search Noise Margin, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2008 (PDF)
  55. Y. Liu, F. Sun and T. Zhang, Energy-Efficient Soft-Output Trellis Decoder Design Using Trellis Quasi-Reduction and Importance-Aware Clock Skew, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2008 (PDF)
  56. R. Dani, T. Zhang and J. Woods, Image Processing Assisted Voltage Overscaling for Energy Efficient IC Realization of Motion Estimation, Visual Communications and Image Processing (VCIP), Jan. 2008 (PDF)(invited)
  57. S. Li and T. Zhang, Hybrid Resistor/FET-Logic Demultiplexer Architecture Design for Hybrid CMOS/Nanodevice Circuits, IEEE International Conference on Computer Design (ICCD), Oct. 2007 (PDF)
  58. Y. Xin, A. Mujitaba, and T. Zhang, Turbo- and LDPC-Coded MIMO-OFDM Systems: A Comparative Study, International Symposium on Personal Indoor and Mobile radio Communications (PIMRC), Sept. 2007
  59. Y. Liu and T. Zhang, On the Selection of Arithmetic Unit Structure in Voltage Overscaled Soft Digital Signal Processing, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2007 (PDF)
  60. S. Chen and T. Zhang, Low Power Soft-Output Signal Detector Design for Wireless MIMO Communication Systems, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2007 (PDF) (Nominated for Best Paper Award)
  61. Y. Liu, T. Zhang, and J. Hu, Soft Clock Skew Scheduling for System-Level Variation Tolerance in Digital Signal Processing Circuits, IEEE International Symposium on Quality Electronic Design (ISQED), March 2007
  62. F. Sun, K. Rose, and T. Zhang, On the Use of Strong BCH Codes for Improving Multilevel NAND Flash Memory Storage Capacity, IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2006 (PDF)
  63. Y. Liu, T. Zhang, and J. Hu, Low Power Trellis Decoder with Overscaled Supply Voltage, IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2006 (PDF)
  64. S. Chen, F. Sun, and T. Zhang, Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006 (PDF)
  65. H. Zhong, T. Zhang, and E. F. Haratsch, VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006
  66. F. Sun and T. Zhang, Two Fault Tolerance Design Approaches for Hybrid CMOS/Nanodevice Digital Memories, IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (Nanoarch), June 2006 (PDF)
  67. S. Chen, T. Zhang, and M. Goel, Relaxed Tree Search MIMO Signal Detection Algorithm Design and VLSI Implementation, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006 (PDF)
  68. F. Sun, S. Devarajan, K. Rose, and T. Zhang, Multilevel Flash Memory On-Chip Error Correction Based on Trellis Coded Modulation, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006 (PDF)
  69. F. Sun and T. Zhang, Low Power State-Parallel Relaxed Adaptive Viterbi Decoder, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006 (PDF)
  70. H. Zhong, T. Zhang, and E. F. Haratsch, High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel with Low Error Floor, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006 (PDF)
  71. K. Zhou, Y. Luo, S. Chen, A. Drake, J. McDonald, and T. Zhang, Triple-Rail MOS Current Mode Logic for High-Speed Self-Timed Pipeline Applications, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2006
  72. S. Chen, T. Zhang, and Y. Xin, Breadth-First Tree Search MIMO Signal Detector Design and VLSI Implementation, Military Communications Conference (MILCOM), Oct. 2005 (PDF)
  73. H. Zhong and T. Zhang, Iterative Max-Log-MAP and LDPC Detector/Decoder Hardware Implementation for Magnetic Read Channel, SRC TECHCON, Oct. 2005
  74. F. Sun and T. Zhang, Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder Design and Implementation, Design Contest winner entry, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2005
  75. K. Zhou, S. Chen, A. Rucinski, J. McDonald, and T. Zhang, Self-timed triple-rail MOS current mode logic pipeline for power-on-demand design, IEEE Midwest Symposium on Circuits and Systems, Aug. 2005
  76. T. Zhang, Y. Xin, and S. Chen, Parallelism/Regularity-Driven MIMO Detection Algorithm Design, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2005 (PDF)
  77. S. Chen and T. Zhang, Run-time Reconfigurable Adaptive Signal Processing System with Asynchronous Dynamic Pipelining: A Case Study of DLMS ADFE, IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2004 (PDF)
  78. T. Zhang, A High Throughput Limited Search Trellis Decoder for Convolutional Code Decoding, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2004 (PDF)
  79. H. Zhong and T. Zhang, Joint Code-Encoder-Decoder Design for LDPC Coding System VLSI Implementation, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2004 (PDF)
  80. T. Zhang, J. Wu and G. J. Saulnier, Efficient Coherent Detector VLSI Design for Continuous Phase Modulation, IEEE Asilomar Conference on Signals, Systems, and Computers, Nov. 2003 (PDF)
  81. H. Zhong and T. Zhang, Design of VLSI Implementation-Oriented LDPC Codes, IEEE Semiannual Vehicular Technology Conference (VTC), Oct. 2003 (PDF)
  82. T. Zhang and K. K. Parhi, A 54 Mbps (3,6)-Regular FPGA LDPC Decoder, Proc. of the 2002 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2002 (PDF)(PS)
  83. T. Zhang and K. K. Parhi, On the High-Speed VLSI Implementation of Errors-and-Erasures Correcting Reed-Solomon Decoders, Proc. of the 12th Great Lakes Symposium on VLSI, April 2002 (PDF)(PS)
  84. T. Zhang and K. K. Parhi, Joint Code and Decoder Design for Implementation-Oriented (3,k)-regular LDPC codes, Proc. of IEEE Asilomar Conference, Nov. 2001 (PDF)(PS)
  85. T. Zhang and K. K. Parhi, High-Performance, Low-Complexity Decoding of Generalized Low-Density Parity-Check Codes, Proc. of Globecom’01, San Antonio, TX, Nov. 2001 (PDF)(PS)
  86. T. Zhang and K. K. Parhi, VLSI Implementation-Oriented (3,k)-regular Low-Density Parity-Check Codes, Proc. of the 2001 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, pp. 25-36, Antwerp, Belgium, Sept. 2001 (PDF)(PS)
  87. T. Zhang, Z. Wang and K. K. Parhi, On Finite Precision Implementation of Low-Density Parity-Check Codes Decoder, Proc. of the 2001 IEEE Int. Symp. on Circuits and Systems (ISCAS), vol. 4, pp. 202-205, Sydney, Australia, May 2001 (PDF)(PS)
  88. T. Zhang and K. K. Parhi, A Class of Efficient-Encoding Generalized Low-Density Parity-Check Codes, Proc. of 2001 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), vol. 4, pp. 2477-2480, Salt Lake City, Utah, May 2001 (PDF)(PS)
  89. T. Zhang and K. K. Parhi, A Novel Systematic Design Approach of Mastrovito Multipliers over GF(2^m), Proc. of the 2000 IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, pp. 507-516, Lafayette, LA, Oct. 2000 (PDF)(PS)

The more you know, the more you learn;

The more you learn, the more you can do;

The more you can do, the more opportunity!

--- Richard W. Hamming